tx2bit.fnf

以LVDS设计为例学习ISE中的时序分析以及低层布局器的使用方法 在底层布局器中对LVDS管脚进行约束的方法

n 61 load_gen_lr0
n 62 ddrc_lrr
n 63 ddrc_lrf
n 64 load_gen_lf1
n 65 load_gen_lf2
n 66 load_gen_lf0
n 67 ddra_lrr
n 68 ddra_lrf
n 69 a
n 70 ddra_qfall
n 71 ddra_qrise
n 72 ddra_qsel
n 73 ddra_crr
n 74 ddra_crf
n 75 b
n 76 ddrb_qfall
n 77 ddrb_qrise
n 78 ddrb_qsel
n 79 ddrb_crr
n 80 ddrb_crf
n 81 c
n 82 ddrc_qrise
n 83 ddrc_qsel
n 84 ddrc_crr
n 85 ddrc_crf
n 86 falldata
n 87 falldatb
n 88 idata_13_IBUF
n 89 idata_12_IBUF
n 90 piso2_q<0>
n 91 idata_9_IBUF
n 92 piso2_q<1>
n 93 idata_5_IBUF
n 94 piso2_q<2>
n 95 piso1_q<0>
n 96 idata_11_IBUF
n 97 piso1_q<1>
n 98 idata_7_IBUF
n 99 piso1_q<2>
n 100 lr
n 101 piso4_q<0>
n 102 idata_8_IBUF
n 103 piso4_q<1>
n 104 idata_4_IBUF
n 105 piso4_q<2>
n 106 lf
n 107 clk4x_BUFGP
end
hnode * tx2bit_map c 4
 area CLB_R61C86:CLB_R64C90
s clk4x_BUFGP BUFG c 1
 p IN I 47
 p OUT O 107
s clk_BUFGP BUFG c 1
 p IN I 49
 p OUT O 51
s piso3_FDC4 FFY c 1
 p C I 107
 p D I 1
 p Q O 57
s piso1_FDC4 FFX c 1
 p C I 107
 p D I 2
 p Q O 52
s piso4_FDC1 FFY c 1
 p C I 107
 p D I 54
 p Q O 105
s piso4_FDC2 FFX c 1
 p C I 107
 p D I 41
 p Q O 103
s piso4_FDC3 FFY c 1
 p C I 107
 p D I 40
 p Q O 101
s piso3_FDC1 FFY c 1
 p C I 107
 p D I 59
 p Q O 58
s piso3_FDC2 FFX c 1
 p C I 107
 p D I 4
 p Q O 43
s piso3_FDC3 FFY c 1
 p C I 107
 p D I 3
 p Q O 42
s piso2_FDC1 FFY c 1
 p C I 107
 p D I 50
 p Q O 94
s piso2_FDC2 FFX c 1
 p C I 107
 p D I 37
 p Q O 92
s piso2_FDC3 FFY c 1
 p C I 107
 p D I 36
 p Q O 90
s piso1_FDC1 FFY c 1
 p C I 107
 p D I 53
 p Q O 99
s piso1_FDC2 FFX c 1
 p C I 107
 p D I 39
 p Q O 97
s piso1_FDC3 FFY c 1
 p C I 107
 p D I 38
 p Q O 95
s load_gen_load_FDR2 FFY c 1
 p C I 107
 p D I 60
 p Q O 100
 p CLR I 100
s load_gen_load_FDR1 FFY c 1
 p C I 107
 p D I 61
 p Q O 60
 p CLR I 100
s load_gen_load_FDC1 FFY c 1
 p C I 51
 p Q O 61
 p CLR I 100
s load_gen_load_FDR_1 FFY c 1
 p C I 107
 p D I 64
 p Q O 65
 p CLR I 65
s load_gen_load_LDC_1 FFY c 1
 p C I 107
 p D I 66
 p Q O 64
 p CLR I 65
s load_gen_load_FDC2 FFY c 1
 p C I 51
 p Q O 66
 p CLR I 65
s load_gen_load_FD_1 FFY c 1
 p C I 107
 p D I 65
 p Q O 106
s piso4_FDC4 FFX c 1
 p C I 107
 p D I 35
 p Q O 87
s piso2_FDC4 FFY c 1
 p C I 107
 p D I 34
 p Q O 86
s ddrc_ddr_fd1 FFY c 1
 p C I 107
 p Q O 82
s ddrc_ddr_ld1 FFY c 1
 p C I 107
 p D I 63
 p Q O 62
s ddrc_ddr_ld2 FFY c 1
 p C I 107
 p D I 62
 p Q O 63
s ddrc_ddr_fd3 FFY c 1
 p C I 107
 p D I 62
 p Q O 84
s ddrc_ddr_fd4 FFY c 1
 p C I 107
 p D I 63
 p Q O 85
s ddrb_ddr_fd1 FFY c 1
 p C I 107
 p D I 57
 p Q O 77
s ddrb_ddr_fd2 FFY c 1
 p C I 107
 p D I 87
 p Q O 76
s ddrb_ddr_ld1 FFY c 1
 p C I 107
 p D I 55
 p Q O 56
s ddrb_ddr_ld2 FFY c 1
 p C I 107
 p D I 56
 p Q O 55
s ddrb_ddr_fd3 FFY c 1
 p C I 107
 p D I 56
 p Q O 79
s ddrb_ddr_fd4 FFY c 1
 p C I 107
 p D I 55
 p Q O 80
s ddra_ddr_fd1 FFY c 1
 p C I 107
 p D I 52
 p Q O 71
s ddra_ddr_fd2 FFY c 1
 p C I 107
 p D I 86
 p Q O 70
s ddra_ddr_ld1 FFY c 1
 p C I 107
 p D I 68
 p Q O 67
s ddra_ddr_ld2 FFY c 1
 p C I 107
 p D I 67
 p Q O 68
s ddra_ddr_fd3 FFY c 1
 p C I 107
 p D I 67
 p Q O 73
s ddra_ddr_fd4 FFY c 1
 p C I 107
 p D I 68
 p Q O 74
s piso4_mux3_U3 FGF c 1
 p I0 I 106
 p I1 I 105
 p I2 I 104
 p O O 41
s piso4_mux2_U3 FGG c 1
 p I0 I 106
 p I1 I 103
 p I2 I 102
 p O O 40
s piso4_mux1_U3 FGF c 1
 p I0 I 106
 p I1 I 101
 p I2 I 89
 p O O 35
s piso3_mux3_U3 FGF c 1
 p I0 I 100
 p I1 I 58
 p I2 I 48
 p O O 4
s piso3_mux2_U3 FGG c 1
 p I0 I 100
 p I1 I 43
 p I2 I 46
 p O O 3
s piso3_mux1_U3 FGG c 1
 p I0 I 100
 p I1 I 42
 p I2 I 45
 p O O 1
s piso2_mux3_U3 FGF c 1
 p I0 I 106
 p I1 I 94
 p I2 I 93
 p O O 37
s piso2_mux2_U3 FGG c 1
 p I0 I 106
 p I1 I 92
 p I2 I 91
 p O O 36
s piso2_mux1_U3 FGG c 1
 p I0 I 106
 p I1 I 90
 p I2 I 88
 p O O 34
s piso1_mux3_U3 FGF c 1
 p I0 I 100
 p I1 I 99
 p I2 I 98
 p O O 39
s piso1_mux2_U3 FGG c 1
 p I0 I 100
 p I1 I 97
 p I2 I 96
 p O O 38
s piso1_mux1_U3 FGF c 1
 p I0 I 100
 p I1 I 95
 p I2 I 44
 p O O 2
s ddrc_ddr_fmap FGF c 1
 p I0 I 85
 p I1 I 84
 p O O 83
s ddrb_ddr_fmap FGF c 1
 p I0 I 80
 p I1 I 79
 p O O 78
s ddra_ddr_fmap FGF c 1
 p I0 I 74
 p I1 I 73
 p O O 72
s ddrc_ddr_m_U3 FGG c 1
 p I0 I 83
 p I1 I 82
 p O O 81
s ddrb_ddr_m_U3 FGG c 1
 p I0 I 78
 p I1 I 77
 p I2 I 76
 p O O 75
s ddra_ddr_m_U3 FGG c 1
 p I0 I 72
 p I1 I 71
 p I2 I 70
 p O O 69
s idata<15> IOB c 1
 ext
 p I O 44
 p PAD X 7
 p IBUFOUT X 44
s idata<14> IOB c 1
 ext
 p I O 45
 p PAD X 8
 p IBUFOUT X 45
s idata<13> IOB c 1
 ext
 p I O 88
 p PAD X 9
 p IBUFOUT X 88
s idata<12> IOB c 1
 ext
 p I O 89
 p PAD X 10
 p IBUFOUT X 89
s idata<11> IOB c 1
 ext
 p I O 96
 p PAD X 11
 p IBUFOUT X 96
s idata<10> IOB c 1
 ext
 p I O 46
 p PAD X 12
 p IBUFOUT X 46
s idata<9> IOB c 1
 ext
 p I O 91
 p PAD X 14
 p IBUFOUT X 91
s idata<8> IOB c 1
 ext
 p I O 102
 p PAD X 15
 p IBUFOUT X 102
s idata<7> IOB c 1
 ext
 p I O 98
 p PAD X 16
 p IBUFOUT X 98
s idata<6> IOB c 1
 ext
 p I O 48
 p PAD X 17
 p IBUFOUT X 48
s idata<5> IOB c 1
 ext
 p I O 93
 p PAD X 18
 p IBUFOUT X 93
s idata<4> IOB c 1
 ext
 p I O 104
 p PAD X 19
 p IBUFOUT X 104
s idata<3> IOB c 1
 ext
 p I O 53
 p PAD X 20
 p IBUFOUT X 53
s idata<2> IOB c 1
 ext
 p I O 59
 p PAD X 21
 p IBUFOUT X 59
s idata<1> IOB c 1
 ext
 p I O 50
 p PAD X 22
 p IBUFOUT X 50
s idata<0> IOB c 1
 ext
 p I O 54
 p PAD X 23
 p IBUFOUT X 54
s db_x IOB c 1
 ext
 pref P118
 p O I 75
 p PAD X 25
 p OBUFIN X 75
s db IOB c 1
 ext
 pref P117
 p O I 75
 p PAD X 26
 p OBUFIN X 75
s da_x IOB c 1
 ext
 pref P111
 p O I 69
 p PAD X 29
 p OBUFIN X 69
s da IOB c 1
 ext
 pref P110
 p O I 69
 p PAD X 30
 p OBUFIN X 69
s clk4x CLKIOB c 1
 ext
 p GCLKOUT O 47
 p PAD X 13
 p IBUFOUT X 47
s clk CLKIOB c 1
 ext
 p GCLKOUT O 49
 p PAD X 24
 p IBUFOUT X 49
s ck_x IOB c 1
 ext
 pref P114
 p O I 81
 p PAD X 27
 p OBUFIN X 81
s ck IOB c 1
 ext
 pref P113
 p O I 81
 p PAD X 28
 p OBUFIN X 81
end
end