tx2bit.syr

以LVDS设计为例学习ISE中的时序分析以及低层布局器的使用方法 在底层布局器中对LVDS管脚进行约束的方法

   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <inv_lrf> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <qsel> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M0> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <M1> may hinder timing optimization.
   You may achieve better results by removing this property
WARNING:Xst:387 - The KEEP property attached to the net <O> may hinder timing optimization.
   You may achieve better results by removing this property
=========================================================================
Final Results
Top Level Output File Name         : tx2bit
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : virtexe
Keep Hierarchy                     : YES
Macro Generator                    : macro+

Design Statistics
# IOs                              : 8

Cell Usage :
# BELS                             : 25
#      GND                         : 16
#      INV                         : 4
#      LUT1                        : 3
#      VCC                         : 2
# FlipFlops/Latches                : 41
#      FD                          : 6
#      FD_1                        : 7
#      FDC                         : 18
#      FDR                         : 2
#      FDR_1                       : 1
#      LD                          : 3
#      LD_1                        : 3
#      LDC_1                       : 1
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 6
#      OBUF_LVDS                   : 6
# Logical                          : 48
#      AND2                        : 15
#      AND2b1                      : 15
#      OR2                         : 15
#      XOR2                        : 3
# Others                           : 18
#      FMAP                        : 18
=========================================================================


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk4x                              | BUFGP                  | 7     |
clk                                | BUFGP                  | 1     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 7.752ns (Maximum Frequency: 128.999MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 9.351ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk4x'
Delay:               3.876ns (Levels of Logic = 1)
  Source:            ddrb/ddr_ld2
  Destination:       ddrb/ddr_ld1
  Source Clock:      clk4x rising
  Destination Clock: clk4x falling

  Data Path: ddrb/ddr_ld2 to ddrb/ddr_ld1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    LD_1:G->Q              2   1.091   1.072  ddr_ld2 (lrf)
    INV:I->O               1   0.468   0.920  ddr_inv (inv_lrf)
    LD:D                       0.325          ddr_ld1
    ----------------------------------------
    Total                      3.876ns (1.884ns logic, 1.992ns route)
                                       (48.6% logic, 51.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk4x'
Offset:              9.351ns (Levels of Logic = 5)
  Source:            ddrc/ddr_fd4
  Destination:       ck_x
  Source Clock:      clk4x rising

  Data Path: ddrc/ddr_fd4 to ck_x
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    FD_1:C->Q              1   0.992   0.920  ddr_fd4 (crf)
    XOR2:I0->O             2   0.468   1.072  ddr_xor (qsel)
     begin scope: 'ddr_m'
    AND2:I0->O             1   0.468   0.920  U1 (M1)
    OR2:I0->O              2   0.468   1.072  U2 (o)
     end scope: 'ddr_m'
     end scope: 'ddrc'
    LUT1:I0->O             1   0.468   0.920  I_INV_c (cn)
    OBUF_LVDS:I->O             1.583          data_cn (ck_x)
    ----------------------------------------
    Total                      9.351ns (4.447ns logic, 4.904ns route)
                                       (47.6% logic, 52.4% route)

=========================================================================
CPU : 5.86 / 6.11 s | Elapsed : 6.00 / 6.00 s
 
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