tx2bit.tlg

以LVDS设计为例学习ISE中的时序分析以及低层布局器的使用方法 在底层布局器中对LVDS管脚进行约束的方法

Selecting top level module tx2bit
Synthesizing module GND
Synthesizing module VCC
Synthesizing module INV
Synthesizing module FDC
@E:"E:\work\6-1\m2_1.v":58:10:58:11|Reference to undefined module AND2B1
@E:"E:\work\6-1\m2_1.v":59:10:59:11|Reference to undefined module AND2
@E:"E:\work\6-1\m2_1.v":60:10:60:11|Reference to undefined module OR2
@E:"E:\work\6-1\m2_1.v":61:10:61:11|Reference to undefined module FMAP
Synthesizing module m2_1
@W:"E:\work\6-1\m2_1.v":58:10:58:11|Creating black_box for AND2B1
Making port I0 a bidir
[0:0]    0: [0:0] Making port I1 a bidir
[0:0]    0: [0:0] Making port O a bidir
[0:0] @W:"E:\work\6-1\m2_1.v":59:10:59:11|Creating black_box for AND2
Making port I0 a bidir
[0:0]    0: [0:0]    1: [0:0]       0: [0:0]          -------
Making port I1 a bidir
[0:0]    0: [0:0] Making port O a bidir
[0:0] @W:"E:\work\6-1\m2_1.v":60:10:60:11|Creating black_box for OR2
Making port I0 a bidir
[0:0]    0: [0:0]       0: [0:0]          -------
Making port I1 a bidir
[0:0]    0: [0:0]       0: [0:0]          -------
Making port O a bidir
[0:0] @W:"E:\work\6-1\m2_1.v":61:10:61:11|Creating black_box for FMAP
Making port I1 a bidir
[0:0]    0: [0:0]    1: [0:0]       0: [0:0]          -------
Making port I2 a bidir
[0:0]    0: [0:0]       0: [0:0]          -------
Making port I3 a bidir
[0:0]    0: [0:0]    1: [0:0]       0: [0:0]          -------
   2: [0:0]       0: [0:0]          -------
Making port I4 a bidir
[0:0]    0: [0:0]    1: [0:0]       0: [0:0]          -------
Making port O a bidir
[0:0]    0: [0:0]       0: [0:0]          -------
Synthesizing module piso
Synthesizing module FDR
Synthesizing module LDC_1
Synthesizing module FDR_1
Synthesizing module FD_1
Synthesizing module load_gen
Synthesizing module FD
Synthesizing module LD
Synthesizing module LD_1
@E:"E:\work\6-1\ddrfd.v":60:5:60:11|Reference to undefined module XOR2
@E:"E:\work\6-1\ddrfd.v":61:6:61:13|Reference to undefined module FMAP
Synthesizing module ddrfd
@W:"E:\work\6-1\ddrfd.v":60:5:60:11|Creating black_box for XOR2
Making port O a bidir
[0:0] Making port I0 a bidir
[0:0]    0: [0:0]       0: [0:0]          -------
Making port I1 a bidir
[0:0]    0: [0:0]       0: [0:0]          -------
Synthesizing module OBUF_LVDS
Synthesizing module tx2bit