📄 tx2bit.par
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Select IO Utilization and Usage Summary_______________________________________NR - means Not Required.Each Group of a specific Standard is listed. IO standard (LVDS Vref=NR Vcco=2.50) uses 6 components (6 currently placed). (0 - Inputs, 6 - Outputs, 0 - Bidirectional)IO standard (LVTTL Vref=NR Vcco=3.30) uses 2 components (2 currently placed). (2 - Inputs, 0 - Outputs, 0 - Bidirectional)Bank Summary____________If an IOB is placed in a Vref site, it will be indicated by the word 'Vref' at
the end of a summary row. IOBs can be placed in a bank's Vref sites when none of
the IOBs in the bank require a Vref site.NR - means Not RequiredBank 0 has 19 pads, 1 (5%) are utilized, with 7 possible dedicated Vref sites.Vref should be set to NR volts. Name IO Select Std Vref Vcco Pad Pin ---- -- ---------- ------ ------ ------ ------ clk I LVTTL NR 3.30 GCLKPAD3 P213 None
Bank 4 has 21 pads, 6 (28%) are utilized, with 7 possible dedicated Vref sites.Vcco should be set to 2.50 volts. Name IO Select Std Vref Vcco Pad Pin ---- -- ---------- ------ ------ ------ ------ db_x O LVDS 2.50 PAD385 P118 None db O LVDS 2.50 PAD386 P117 None ck_x O LVDS 2.50 PAD407 P114 None ck O LVDS 2.50 PAD408 P113 None da_x O LVDS 2.50 PAD409 P111 None
Vref da O LVDS 2.50 PAD410 P110 None Bank 5 has 20 pads, 1 (5%) are utilized, with 7 possible dedicated Vref sites.Vref should be set to NR volts. Name IO Select Std Vref Vcco Pad Pin ---- -- ---------- ------ ------ ------ ------ clk4x I LVTTL NR 3.30 GCLKPAD1 P89 None
Placer completed in real time: 8 secs Dumping design to file tx2bit.ncd.Total REAL time to Placer completion: 8 secs Total CPU time to Placer completion: 4 secs 0 connection(s) routed; 103 unrouted.Starting router resource preassignmentCompleted router resource preassignment. REAL time: 8 secs Starting iterative routing. Routing active signals...........End of iteration 1 103 successful; 0 unrouted; (0) REAL time: 9 secs Constraints are met. Total REAL time: 9 secs Total CPU time: 6 secs End of route. 103 routed (100.00%); 0 unrouted.No errors found. Completely routed. Total REAL time to Router completion: 9 secs Total CPU time to Router completion: 6 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 129The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 0.914 ns The Maximum Pin Delay is: 6.801 ns The Average Connection Delay on the 10 Worst Nets is: 1.891 ns Listing Pin Delays by value: (ns) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 7.00 d >= 7.00 --------- --------- --------- --------- --------- --------- 97 0 0 0 6 0Timing Score: 0Asterisk (*) preceding a constraint indicates it was not met.-------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels-------------------------------------------------------------------------------- NET "ddra/qrise" MAXDELAY = 600 pS | 0.600ns | 0.237ns | -------------------------------------------------------------------------------- NET "ddra/qrise" MAXSKEW = 50 pS | 0.050ns | 0.000ns | -------------------------------------------------------------------------------- NET "ddra/qfall" MAXDELAY = 600 pS | 0.600ns | 0.234ns | -------------------------------------------------------------------------------- NET "ddra/qfall" MAXSKEW = 50 pS | 0.050ns | 0.000ns | -------------------------------------------------------------------------------- NET "ddra/crr" MAXDELAY = 600 pS | 0.600ns | 0.364ns | -------------------------------------------------------------------------------- NET "ddra/crf" MAXDELAY = 600 pS | 0.600ns | 0.438ns | -------------------------------------------------------------------------------- NET "ddrb/qrise" MAXDELAY = 600 pS | 0.600ns | 0.537ns | -------------------------------------------------------------------------------- NET "ddrb/qrise" MAXSKEW = 50 pS | 0.050ns | 0.000ns | -------------------------------------------------------------------------------- NET "ddrb/qfall" MAXDELAY = 600 pS | 0.600ns | 0.361ns | -------------------------------------------------------------------------------- NET "ddrb/qfall" MAXSKEW = 50 pS | 0.050ns | 0.000ns | -------------------------------------------------------------------------------- NET "ddrb/crr" MAXDELAY = 600 pS | 0.600ns | 0.471ns | -------------------------------------------------------------------------------- NET "ddrb/crf" MAXDELAY = 600 pS | 0.600ns | 0.385ns | -------------------------------------------------------------------------------- NET "ddrc/qrise" MAXDELAY = 600 pS | 0.600ns | 0.364ns | -------------------------------------------------------------------------------- NET "ddrc/qrise" MAXSKEW = 50 pS | 0.050ns | 0.000ns | -------------------------------------------------------------------------------- NET "ddrc/crr" MAXDELAY = 600 pS | 0.600ns | 0.234ns | -------------------------------------------------------------------------------- NET "ddrc/crf" MAXDELAY = 600 pS | 0.600ns | 0.450ns | -------------------------------------------------------------------------------- TS_clk4x = PERIOD TIMEGRP "clk4x" 2 nS | | | HIGH 50.000000 % | | | -------------------------------------------------------------------------------- TS_clk = PERIOD TIMEGRP "clk" 8 nS HIG | | | H 50.000000 % | | | -------------------------------------------------------------------------------- TS_FST2FST = MAXDELAY FROM TIMEGRP "FASTC | 3.800ns | 2.911ns | 2 LOCK" TO TIMEGRP "FASTCLOCK" 3.800 nS | | | -------------------------------------------------------------------------------- TS_FST2LAT = MAXDELAY FROM TIMEGRP "FASTC | | | LOCK" TO TIMEGRP "FASELATCH" 3.800 nS | | | -------------------------------------------------------------------------------- TS_LAT2LAT = MAXDELAY FROM TIMEGRP "FASEL | 3.800ns | 2.283ns | 2 ATCH" TO TIMEGRP "FASELATCH" 3.800 nS | | | -------------------------------------------------------------------------------- TS_SLO2FST = MAXDELAY FROM TIMEGRP "SLOWC | 8.000ns | 2.482ns | 2 LOCK" TO TIMEGRP "FASTCLOCK" 8 nS | | | --------------------------------------------------------------------------------All constraints were met.Dumping design to file tx2bit.ncd.All signals are completely routed.Total REAL time to PAR completion: 11 secs Total CPU time to PAR completion: 7 secs Placement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - No errors found.PAR done.⌨️ 快捷键说明
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