📄 tx2bit.mrp
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Release 4.2i - Map E.35Xilinx Mapping Report File for Design 'tx2bit'Design Information------------------Command Line : map -p xcv1000e-hq240-6 -cm area -detail -k 4 -c 100 -tx off
tx2bit.ngd Target Device : xv1000eTarget Package : hq240Target Speed : -6Mapper Version : virtexe -- $Revision: 1.58 $Mapped Date : Tue Dec 17 10:05:34 2002Design Summary-------------- Number of errors: 0 Number of warnings: 2 Number of Slices: 36 out of 12,288 1% Number of Slices containing unrelated logic: 0 out of 36 0% Total Number Slice Registers: 38 out of 24,576 1% Number used as Flip Flops: 31 Number used as Latches: 7 Number of 4 input LUTs: 17 out of 24,576 1% Number of bonded IOBs: 6 out of 158 3% Number of GCLKs: 2 out of 4 50% Number of GCLKIOBs: 2 out of 4 50%Total equivalent gate count for design: 385Additional JTAG gate count for IOBs: 384Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:MapLib:39 - The timing specification "MAXDELAY=600.000000 pS" on net
"ddrc/qfall" has been discarded, because the net was optimized out of the
design.WARNING:MapLib:39 - The timing specification "MAXSKEW=50.000000 pS" on net
"ddrc/qfall" has been discarded, because the net was optimized out of the
design.Section 3 - Informational-------------------------INFO:MapLib:62 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.Section 4 - Removed Logic Summary--------------------------------- 15 block(s) removed 9 block(s) optimized away 15 signal(s) removed 7 Block(s) redundantSection 5 - Removed Logic-------------------------The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).The signal "ddra/ddr_m/w_LO" is sourceless and has been removed.The signal "ddrb/ddr_m/w_LO" is sourceless and has been removed.The signal "ddrc/ddr_m/w_LO" is sourceless and has been removed.The signal "piso1/mux1/w_LO" is sourceless and has been removed.The signal "piso1/mux2/w_LO" is sourceless and has been removed.The signal "piso1/mux3/w_LO" is sourceless and has been removed.The signal "piso2/mux1/w_LO" is sourceless and has been removed.The signal "piso2/mux2/w_LO" is sourceless and has been removed.The signal "piso2/mux3/w_LO" is sourceless and has been removed.The signal "piso3/mux1/w_LO" is sourceless and has been removed.The signal "piso3/mux2/w_LO" is sourceless and has been removed.The signal "piso3/mux3/w_LO" is sourceless and has been removed.The signal "piso4/mux1/w_LO" is sourceless and has been removed.The signal "piso4/mux2/w_LO" is sourceless and has been removed.The signal "piso4/mux3/w_LO" is sourceless and has been removed.Unused block "ddra/ddr_m/U_gnd" (ZERO) removed.Unused block "ddrb/ddr_m/U_gnd" (ZERO) removed.Unused block "ddrc/ddr_m/U_gnd" (ZERO) removed.Unused block "piso1/mux1/U_gnd" (ZERO) removed.Unused block "piso1/mux2/U_gnd" (ZERO) removed.Unused block "piso1/mux3/U_gnd" (ZERO) removed.Unused block "piso2/mux1/U_gnd" (ZERO) removed.Unused block "piso2/mux2/U_gnd" (ZERO) removed.Unused block "piso2/mux3/U_gnd" (ZERO) removed.Unused block "piso3/mux1/U_gnd" (ZERO) removed.Unused block "piso3/mux2/U_gnd" (ZERO) removed.Unused block "piso3/mux3/U_gnd" (ZERO) removed.Unused block "piso4/mux1/U_gnd" (ZERO) removed.Unused block "piso4/mux2/U_gnd" (ZERO) removed.Unused block "piso4/mux3/U_gnd" (ZERO) removed.Optimized Block(s):TYPE BLOCKGND GND_IVCC U_vccFD_1 ddrc/ddr_fd2VCC load_gen/U_vccFDC piso2/FDC1FDC piso2/FDC2OR2 piso2/mux3/U2AND2b1 piso2/mux3/U0AND2 piso2/mux3/U1Redundant Block(s):TYPE BLOCKINV ddra/ddr_invINV ddrb/ddr_invINV ddrc/ddr_invLUT1 I_INV_aLUT1 I_INV_bLUT1 I_INV_cINV inv_clkSection 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk | GCLKIOB | INPUT | LVTTL | | | | | || clk4x | GCLKIOB | INPUT | LVTTL | | | | | || ck | IOB | OUTPUT | LVDS | | | | | || ck_x | IOB | OUTPUT | LVDS | | | | | || da | IOB | OUTPUT | LVDS | | | | | || da_x | IOB | OUTPUT | LVDS | | | | | || db | IOB | OUTPUT | LVDS | | | | | || db_x | IOB | OUTPUT | LVDS | | | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.⌨️ 快捷键说明
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