tx2bit.twr

以LVDS设计为例学习ISE中的时序分析以及低层布局器的使用方法 在底层布局器中对LVDS管脚进行约束的方法

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Release 4.2i - Trace E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

trce -e 3 -l 3 -xml tx2bit tx2bit.ncd -o tx2bit.twr tx2bit.pcf

Design file:              tx2bit.ncd
Physical constraint file: tx2bit.pcf
Device,speed:             xcv1000e,-6 (PRELIMINARY 1.65 2001-12-19)
Report level:             error report
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================================================================================
Timing constraint: NET "ddra/qrise" MAXDELAY = 600 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net delay is   0.385ns.
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================================================================================
Timing constraint: NET "ddra/qrise" MAXSKEW = 50 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net skew is   0.000ns.
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================================================================================
Timing constraint: NET "ddra/qfall" MAXDELAY = 600 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net delay is   0.364ns.
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================================================================================
Timing constraint: NET "ddra/qfall" MAXSKEW = 50 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net skew is   0.000ns.
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================================================================================
Timing constraint: NET "ddra/crr" MAXDELAY = 600 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net delay is   0.365ns.
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================================================================================
Timing constraint: NET "ddra/crf" MAXDELAY = 600 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net delay is   0.237ns.
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================================================================================
Timing constraint: NET "ddrb/qrise" MAXDELAY = 600 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net delay is   0.237ns.
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================================================================================
Timing constraint: NET "ddrb/qrise" MAXSKEW = 50 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net skew is   0.000ns.
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================================================================================
Timing constraint: NET "ddrb/qfall" MAXDELAY = 600 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net delay is   0.234ns.
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================================================================================
Timing constraint: NET "ddrb/qfall" MAXSKEW = 50 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net skew is   0.000ns.
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================================================================================
Timing constraint: NET "ddrb/crr" MAXDELAY = 600 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net delay is   0.376ns.
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================================================================================
Timing constraint: NET "ddrb/crf" MAXDELAY = 600 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net delay is   0.364ns.
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================================================================================
Timing constraint: NET "ddrc/qrise" MAXDELAY = 600 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net delay is   0.361ns.
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================================================================================
Timing constraint: NET "ddrc/qrise" MAXSKEW = 50 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net skew is   0.000ns.
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================================================================================
Timing constraint: NET "ddrc/crr" MAXDELAY = 600 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net delay is   0.237ns.
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================================================================================
Timing constraint: NET "ddrc/crf" MAXDELAY = 600 pS  ;

 1 item analyzed, 0 timing errors detected.
 Maximum net delay is   0.234ns.
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================================================================================
Timing constraint: TS_clk4x = PERIOD TIMEGRP "clk4x"  3.200 nS   HIGH 50.000000 % ;

 0 items analyzed, 0 timing errors detected.
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================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk"  12.800 nS   HIGH 50.000000 % ;

 0 items analyzed, 0 timing errors detected.
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================================================================================
Timing constraint: TS_FST2FST = MAXDELAY FROM TIMEGRP "FASTCLOCK" TO TIMEGRP "FASTCLOCK" 3.800 nS ;

 37 items analyzed, 0 timing errors detected.
 Minimum period is   4.740ns.
 Maximum delay is   2.955ns.
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================================================================================
Timing constraint: TS_FST2LAT = MAXDELAY FROM TIMEGRP "FASTCLOCK" TO TIMEGRP "FASELATCH" 3.800 nS ;

 0 items analyzed, 0 timing errors detected.
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================================================================================
Timing constraint: TS_LAT2LAT = MAXDELAY FROM TIMEGRP "FASELATCH" TO TIMEGRP "FASELATCH" 3.800 nS ;

 6 items analyzed, 0 timing errors detected.
 Minimum period is   4.688ns.
 Maximum delay is   2.344ns.
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================================================================================
Timing constraint: TS_SLO2FST = MAXDELAY FROM TIMEGRP "SLOWCLOCK" TO TIMEGRP "FASTCLOCK" 8 nS  ; 

 2 items analyzed, 0 timing errors detected.
 Maximum delay is   2.292ns.
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All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk4x
---------------+------------+------------+
               |  Setup to  |  Hold to   |
Source Pad     | clk (edge) | clk (edge) |
---------------+------------+------------+
clk            |    2.292(R)|    0.000(R)|
---------------+------------+------------+

Clock to Setup on destination clock clk4x
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk4x          |    2.955|    2.370|    2.344|    2.867|
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 45 paths, 11 nets, and 90 connections (87.4% coverage)

Design statistics:
   Minimum period:   4.740ns (Maximum frequency: 210.970MHz)
   Maximum path delay from/to any node:   2.955ns
   Maximum net delay:   0.385ns


Analysis completed Sun Dec 15 15:41:47 2002
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