tx2bit.v

以LVDS设计为例学习ISE中的时序分析以及低层布局器的使用方法 在底层布局器中对LVDS管脚进行约束的方法

//+FHDR---------------------------------------------------------------------
// Copyright (c) 2002, zte.
// zte Confidential Proprietary
// --------------------------------------------------------------------------
// FILE NAME :tx2bit.v
// TYPE : module
// DEPARTMENT :
// AUTHOR : Xue Xiaogang 
// AUTHOR'S EMAIL : [e-mail]
// --------------------------------------------------------------------------
// Release history
// 
//   v00  2002-5-28 16:18  gen.
// --------------------------------------------------------------------------
// KEYWORDS : 
// --------------------------------------------------------------------------
// PURPOSE :   
//
// --------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME            RANGE : DESCRIPTION        : DEFAULT : VA UNITS
//  
// --------------------------------------------------------------------------
// REUSE ISSUES
// reset_b_b Strategy :
// Clock Domains :
// Critical Timing :
// Test Features :
// Asynchronous I/F :
// Instantiations :
// Function and task used :
// Other : 
//-FHDR--------------------------------------------------------------------


module tx2bit(
    da,
    da_x,
    ck,
    ck_x,
    db,
    db_x,
    clk,
    clk4x,
//    idata
    );

output da;
output da_x;
output ck;
output ck_x;
output db;
output db_x;

input clk;
input clk4x;
//input [15:0] idata;
wire [15:0] idata = 16'habcd;

GND  U_gnd  ( .G( w_LO  )  );    
VCC  U_vcc  ( .P( w_HI  )  );

wire [3:0] data_piso1;
wire [3:0] data_piso2;
wire [3:0] data_piso3;
wire [3:0] data_piso4;

assign data_piso1 = {idata[3],idata[7],idata[11],idata[15]};
assign data_piso2 = {idata[1],idata[5],idata[9], idata[13]};
assign data_piso3 = {idata[2],idata[6],idata[10],idata[14]};
assign data_piso4 = {idata[0],idata[4],idata[8], idata[12]};

//--------------------------------------piso------------------------------------
INV inv_clk(.I(clk4x),.O(inv_clk4x));
piso piso1(.o(risedata) ,.clk4x(clk4x),     .clr(w_LO), .load(lr), .d(data_piso1));
piso piso2(.o(falldata) ,.clk4x(inv_clk4x), .clr(w_LO), .load(lf), .d(data_piso2));
piso piso3(.o(risedatb) ,.clk4x(clk4x),     .clr(w_LO), .load(lr), .d(data_piso3));
piso piso4(.o(falldatb) ,.clk4x(inv_clk4x), .clr(w_LO), .load(lf), .d(data_piso4));
    
//--------------------------------------load gen--------------------------------
load_gen load_gen(.clk(clk),.clk4x(clk4x),.loadrise(lr),.loadfall(lf));

//-------------------------------------ddrfd------------------------------------
ddrfd ddra (.q(a), .clk(clk4x), .d0(risedata), .d1(falldata));    
ddrfd ddrc (.q(c), .clk(clk4x), .d0(w_HI),     .d1(w_LO)    );    
ddrfd ddrb (.q(b), .clk(clk4x), .d0(risedatb), .d1(falldatb));

//-------------------------------------LVDS port--------------------------------
wire an;
wire bn;
wire cn;

OBUF_LVDS data_a      (.I(a), .O(da)); 
assign an = !a; 
OBUF_LVDS data_an     (.I(an), .O(da_x)); 

OBUF_LVDS data_c      (.I(c), .O(ck)); 
assign cn = !c; 
OBUF_LVDS data_cn     (.I(cn), .O(ck_x)); 

OBUF_LVDS data_b      (.I(b), .O(db)); 
assign bn = !b; 
OBUF_LVDS data_bn     (.I(bn), .O(db_x)); 

//-----------------------------------test output ------------------------------
//wire da;
//wire ck;
//wire db;

//assign da = a;
//assign ck = c;
//assign db = b;

  
endmodule