piso.v

以LVDS设计为例学习ISE中的时序分析以及低层布局器的使用方法 在底层布局器中对LVDS管脚进行约束的方法

//+FHDR---------------------------------------------------------------------
// Copyright (c) 2002, zte.
// zte Confidential Proprietary
// --------------------------------------------------------------------------
// FILE NAME :piso.v
// TYPE : module
// DEPARTMENT :
// AUTHOR : Xue Xiaogang 
// AUTHOR'S EMAIL : [e-mail]
// --------------------------------------------------------------------------
// Release history
// 
//   v00  2002-5-28 16:18  gen.
// --------------------------------------------------------------------------
// KEYWORDS : 
// --------------------------------------------------------------------------
// PURPOSE :   Parallel in/Serial out shift Register
//
// --------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME            RANGE : DESCRIPTION        : DEFAULT : VA UNITS
//  
// --------------------------------------------------------------------------
// REUSE ISSUES
// reset_b_b Strategy :
// Clock Domains :
// Critical Timing :
// Test Features :
// Asynchronous I/F :
// Instantiations :
// Function and task used :
// Other : 
//-FHDR--------------------------------------------------------------------

module piso(
    o,
    clk4x,
    clr,
    load,
    d
    );
    
output o;
input clk4x;
input clr;
input load;
input [3:0] d;
    
wire [2:0] q;
wire [2:0] m;

FDC FDC1(.Q(q[2]), .C(clk4x), .CLR(clr), .D(d[3]));
FDC FDC2(.Q(q[1]), .C(clk4x), .CLR(clr), .D(m[2]));
FDC FDC3(.Q(q[0]), .C(clk4x), .CLR(clr), .D(m[1]));
FDC FDC4(.Q(o)   , .C(clk4x), .CLR(clr), .D(m[0]));
    
m2_1 mux1( .d0(q[0]), .d1(d[0]), .s0(load), .o(m[0]));    
m2_1 mux2( .d0(q[1]), .d1(d[1]), .s0(load), .o(m[1]));    
m2_1 mux3( .d0(q[2]), .d1(d[2]), .s0(load), .o(m[2]));    

endmodule

//-----------------------------------end 63----------------------2002-5-28 16:12