📄 module_a.srr
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$ Start of Compile
#Wed Mar 26 20:29:46 2003
Synplicity Verilog Compiler, version 7.2, Build 112R, built Oct 23 2002
Copyright (C) 1994-2002, Synplicity Inc. All Rights Reserved
@I::"J:\Example-8-1\Modular_Design\syn_modules\module_a\module_a.v"
Verilog syntax check successful!
Selecting top level module module_a
Synthesizing module module_a
@END
Process took 0.09 seconds realtime, 0.1 seconds cputime
Synplicity Xilinx Technology Mapper, version 7.2, Build 175R, built Oct 24 2002
Copyright (C) 1994-2002, Synplicity Inc. All Rights Reserved
Net buffering Report for view:work.module_a(verilog):
No nets needed buffering.
@N|The option to pack flops in the IOB has not been specified
Writing Analyst data base J:\Example-8-1\Modular_Design\syn_modules\module_a\rev_1\module_a.srm
Writing EDIF Netlist and constraint files
Found clock module_a|CLK_TOP with period 10.00ns
Found clock module_a|MODA_CLK with period 10.00ns
##### START TIMING REPORT #####
# Timing Report written on Wed Mar 26 20:29:49 2003
#
Top view: module_a
Paths requested: 5
Constraint File(s):
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N| Clock constraints cover all FF-to-FF, FF-to-output, input-to-FF and input-to-output paths associated with a particular clock.
Performance Summary
*******************
Worst slack in design: 7.703
Requested Estimated Requested Estimated Clock
Starting Clock Frequency Frequency Period Period Slack Type
------------------------------------------------------------------------------------------------
module_a|CLK_TOP 100.0 MHz 436.9 MHz 10.000 2.289 7.711 inferred
module_a|MODA_CLK 100.0 MHz 435.3 MHz 10.000 2.297 7.703 inferred
================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------------------
module_a|MODA_CLK module_a|MODA_CLK | 10.000 7.703 | No paths - | No paths - | No paths -
module_a|MODA_CLK module_a|CLK_TOP | 10.000 7.703 | No paths - | No paths - | No paths -
module_a|CLK_TOP module_a|MODA_CLK | 10.000 7.711 | No paths - | No paths - | No paths -
module_a|CLK_TOP module_a|CLK_TOP | 10.000 7.711 | No paths - | No paths - | No paths -
============================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
Input Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
------------------------------------------------------------------------------------------
B2A_IN module_a|MODA_CLK (rising) NA 0.000 9.678 9.678
C2A_IN module_a|MODA_CLK (rising) NA 0.000 9.678 9.678
CLK_TOP NA NA NA NA NA
MODA_CLK NA NA NA NA NA
MODA_DATA module_a|CLK_TOP (rising) NA 0.000 9.678 9.678
TOP2A_IN module_a|CLK_TOP (rising) NA 0.000 9.678 9.678
==========================================================================================
Output Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
--------------------------------------------------------------------------------------------------
A2B_OUT module_a|CLK_TOP (rising) NA 1.012 10.000 8.989
A2C_OUT module_a|MODA_CLK (rising) NA 1.012 10.000 8.989
A2TOP_OBUFT_I_OUT module_a|MODA_CLK (rising) NA 1.012 10.000 8.989
MODA_OUT module_a|CLK_TOP (rising) NA 1.012 10.000 8.989
==================================================================================================
====================================
Detailed Report for Clock: module_a|CLK_TOP
====================================
Starting Points with worst slack
********************************
Arrival
Instance Type Pin Net Time Slack
--------------------------------------------------------------------
Q0_OUT FD Q Q0_OUT 1.160 7.711
Q2_OUT FD Q Q2_OUT 1.160 7.711
A2B_OUT FDR Q A2B_OUT 1.012 8.989
MODA_OUT FDS Q MODA_OUT 1.012 8.989
MODA_DATA Port MODA_DATA MODA_DATA 0.000 9.678
TOP2A_IN Port TOP2A_IN TOP2A_IN 0.000 9.678
====================================================================
Ending Points with worst slack
******************************
Required
Instance Type Pin Net Time Slack
----------------------------------------------------------------------------
A2B_OUT FDR D G_7 9.678 7.711
A2C_OUT FDS D N_11_i 9.678 7.711
A2TOP_OBUFT_I_OUT FDR D G_7 9.678 7.711
MODA_OUT FDS D N_11_i 9.678 7.711
A2B_OUT Port A2B_OUT A2B_OUT 10.000 8.989
MODA_OUT Port MODA_OUT MODA_OUT 10.000 8.989
Q0_OUT FD D MODA_DATA 9.678 9.678
Q2_OUT FD D TOP2A_IN 9.678 9.678
============================================================================
Worst Paths Information
***********************
Path information for path number 1:
- Setup time: 0.322
= Required time: 9.678
- Propagation time: 1.967
= Slack (non-critical) : 7.711
Starting point: Q0_OUT / Q
Ending point: A2B_OUT / D
The start point is clocked by module_a|CLK_TOP [rising] on pin C
The end point is clocked by module_a|CLK_TOP [rising] on pin C
Instance / Net Pin Pin Arrival Fan
Name Type Name Dir Delay Time Out
----------------------------------------------------------------------
Q0_OUT FD Q Out 1.160 1.160
Q0_OUT Net 2
G_7 LUT3 I0 In 1.160
G_7 LUT3 O Out 0.806 1.967
G_7 Net 2
A2B_OUT FDR D In 1.967
======================================================================
====================================
Detailed Report for Clock: module_a|MODA_CLK
====================================
Starting Points with worst slack
********************************
Arrival
Instance Type Pin Net Time Slack
---------------------------------------------------------------------------------
Q3_OUT FD Q Q3_OUT 1.247 7.703
Q1_OUT FD Q Q1_OUT 1.160 7.711
A2C_OUT FDS Q A2C_OUT 1.012 8.989
A2TOP_OBUFT_I_OUT FDR Q A2TOP_OBUFT_I_OUT 1.012 8.989
B2A_IN Port B2A_IN B2A_IN 0.000 9.678
C2A_IN Port C2A_IN C2A_IN 0.000 9.678
=================================================================================
Ending Points with worst slack
******************************
Required
Instance Type Pin Net Time Slack
---------------------------------------------------------------------------------------------
A2B_OUT FDR R Q3_OUT_i 9.756 7.703
A2TOP_OBUFT_I_OUT FDR R Q3_OUT_i 9.756 7.703
A2B_OUT FDR D G_7 9.678 7.711
A2C_OUT FDS D N_11_i 9.678 7.711
A2TOP_OBUFT_I_OUT FDR D G_7 9.678 7.711
MODA_OUT FDS D N_11_i 9.678 7.711
A2C_OUT FDS S Q3_OUT 9.756 8.509
MODA_OUT FDS S Q3_OUT 9.756 8.509
A2C_OUT Port A2C_OUT A2C_OUT 10.000 8.989
A2TOP_OBUFT_I_OUT Port A2TOP_OBUFT_I_OUT A2TOP_OBUFT_I_OUT 10.000 8.989
=============================================================================================
Worst Paths Information
***********************
Path information for path number 1:
- Setup time: 0.244
= Required time: 9.756
- Propagation time: 2.053
= Slack (critical) : 7.703
Starting point: Q3_OUT / Q
Ending point: A2B_OUT / R
The start point is clocked by module_a|MODA_CLK [rising] on pin C
The end point is clocked by module_a|CLK_TOP [rising] on pin C
Instance / Net Pin Pin Arrival Fan
Name Type Name Dir Delay Time Out
----------------------------------------------------------------------
Q3_OUT FD Q Out 1.247 1.247
Q3_OUT Net 3
Q3_OUT_i INV I In 1.247
Q3_OUT_i INV O Out 0.806 2.053
Q3_OUT_i Net 2
A2B_OUT FDR R In 2.053
======================================================================
##### END TIMING REPORT #####
---------------------------------------
Resource Usage Report for module_a
Mapping to part: xc2v40cs144-5
Cell usage:
FD 4 uses
FDR 2 uses
FDS 2 uses
I/O Register bits: 0
Register bits not including I/Os: 8 (1%)
Mapping Summary:
Total LUTs: 2 (0%)
Mapper successful!
Process took 2.243 seconds realtime, 2.283 seconds cputime
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