module_c.edf

一个简单的Modular Design设计,源代码

(edif  module_c
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap
    (keywordLevel 0)
  )
  (status
    (written
      (timeStamp 2003 3 26 12 11 55)
      (program "FPGA Express"
	(version "3.6.0.6613")
      )
      (author "wcheng")
    )
  )
  (external VIRTEX2
    (edifLevel 0)
    (technology
      (numberDefinition)
    )
    (cell FD
      (cellType GENERIC)
      (view Netlist_representation
	(viewType NETLIST)
	(interface
	  (port Q
	    (direction OUTPUT)
	  )
	  (port D
	    (direction INPUT)
	  )
	  (port C
	    (direction INPUT)
	  )
	)
      )
    )
    (cell LUT4
      (cellType GENERIC)
      (view Netlist_representation
	(viewType NETLIST)
	(interface
	  (port I0
	    (direction INPUT)
	  )
	  (port I1
	    (direction INPUT)
	  )
	  (port I2
	    (direction INPUT)
	  )
	  (port I3
	    (direction INPUT)
	  )
	  (port O
	    (direction OUTPUT)
	  )
	)
      )
    )
  )
  (library DESIGNS
    (edifLevel 0)
    (technology
      (numberDefinition)
    )
    (cell module_c
      (cellType GENERIC)
      (view Netlist_representation
	(viewType NETLIST)
	(interface
	  (port CLK_TOP
	    (direction INPUT)
	  )
	  (port TOP2A_C_IN
	    (direction INPUT)
	  )
	  (port B2C_IN
	    (direction INPUT)
	  )
	  (port A2C_IN
	    (direction INPUT)
	  )
	  (port MODC_DATA
	    (direction INPUT)
	  )
	  (port MODC_CLK
	    (direction INPUT)
	  )
	  (port MODC_OUT
	    (direction OUTPUT)
	  )
	  (port C2TOP_OUT
	    (direction OUTPUT)
	  )
	  (port C2AND2_OUT
	    (direction OUTPUT)
	  )
	  (port C2A_OUT
	    (direction OUTPUT)
	  )
	)
	(contents
	  (instance C2TOP_OUT_reg
	    (viewRef Netlist_representation
	      (cellRef FD
		(libraryRef VIRTEX2)
	      )
	    )
	  )
	  (instance C2AND2_OUT_reg
	    (viewRef Netlist_representation
	      (cellRef FD
		(libraryRef VIRTEX2)
	      )
	    )
	  )
	  (instance MODC_OUT_reg
	    (viewRef Netlist_representation
	      (cellRef FD
		(libraryRef VIRTEX2)
	      )
	    )
	  )
	  (instance Q1_OUT_reg
	    (viewRef Netlist_representation
	      (cellRef FD
		(libraryRef VIRTEX2)
	      )
	    )
	  )
	  (instance C2A_OUT_reg
	    (viewRef Netlist_representation
	      (cellRef FD
		(libraryRef VIRTEX2)
	      )
	    )
	  )
	  (instance Q3_OUT_reg
	    (viewRef Netlist_representation
	      (cellRef FD
		(libraryRef VIRTEX2)
	      )
	    )
	  )
	  (instance Q0_OUT_reg
	    (viewRef Netlist_representation
	      (cellRef FD
		(libraryRef VIRTEX2)
	      )
	    )
	  )
	  (instance Q2_OUT_reg
	    (viewRef Netlist_representation
	      (cellRef FD
		(libraryRef VIRTEX2)
	      )
	    )
	  )
	  (instance C18
	    (viewRef Netlist_representation
	      (cellRef LUT4
		(libraryRef VIRTEX2)
	      )
	    )
	    (property lut_function
	      (string "(I0 I1 I2 I3)")
	    )
	    (property INIT
	      (string "8000")
	    )
	    (property EQN
	      (string "(I0 * I1 * I2 * I3)")
	    )
	  )
	  (instance C19
	    (viewRef Netlist_representation
	      (cellRef LUT4
		(libraryRef VIRTEX2)
	      )
	    )
	    (property lut_function
	      (string "(I0 + I1 + I2 + I3)")
	    )
	    (property INIT
	      (string "FFFE")
	    )
	    (property EQN
	      (string "(I0 + I1 + I2 + I3)")
	    )
	  )
	  (net CLK_TOP
	    (joined
	      (portRef CLK_TOP)
	      (portRef C
		(instanceRef C2AND2_OUT_reg)
	      )
	      (portRef C
		(instanceRef MODC_OUT_reg)
	      )
	      (portRef C
		(instanceRef Q0_OUT_reg)
	      )
	      (portRef C
		(instanceRef Q2_OUT_reg)
	      )
	    )
	  )
	  (net TOP2A_C_IN
	    (joined
	      (portRef TOP2A_C_IN)
	      (portRef D
		(instanceRef Q2_OUT_reg)
	      )
	    )
	  )
	  (net B2C_IN
	    (joined
	      (portRef B2C_IN)
	      (portRef D
		(instanceRef Q1_OUT_reg)
	      )
	    )
	  )
	  (net A2C_IN
	    (joined
	      (portRef A2C_IN)
	      (portRef D
		(instanceRef Q3_OUT_reg)
	      )
	    )
	  )
	  (net MODC_DATA
	    (joined
	      (portRef MODC_DATA)
	      (portRef D
		(instanceRef Q0_OUT_reg)
	      )
	    )
	  )
	  (net MODC_CLK
	    (joined
	      (portRef MODC_CLK)
	      (portRef C
		(instanceRef C2TOP_OUT_reg)
	      )
	      (portRef C
		(instanceRef Q1_OUT_reg)
	      )
	      (portRef C
		(instanceRef C2A_OUT_reg)
	      )
	      (portRef C
		(instanceRef Q3_OUT_reg)
	      )
	    )
	  )
	  (net MODC_OUT
	    (joined
	      (portRef MODC_OUT)
	      (portRef Q
		(instanceRef MODC_OUT_reg)
	      )
	    )
	  )
	  (net C2TOP_OUT
	    (joined
	      (portRef C2TOP_OUT)
	      (portRef Q
		(instanceRef C2TOP_OUT_reg)
	      )
	    )
	  )
	  (net C2AND2_OUT
	    (joined
	      (portRef C2AND2_OUT)
	      (portRef Q
		(instanceRef C2AND2_OUT_reg)
	      )
	    )
	  )
	  (net C2A_OUT
	    (joined
	      (portRef C2A_OUT)
	      (portRef Q
		(instanceRef C2A_OUT_reg)
	      )
	    )
	  )
	  (net Q3_OUT
	    (joined
	      (portRef Q
		(instanceRef Q3_OUT_reg)
	      )
	      (portRef I3
		(instanceRef C18)
	      )
	      (portRef I3
		(instanceRef C19)
	      )
	    )
	  )
	  (net OR4_OUT
	    (joined
	      (portRef D
		(instanceRef C2TOP_OUT_reg)
	      )
	      (portRef D
		(instanceRef MODC_OUT_reg)
	      )
	      (portRef O
		(instanceRef C19)
	      )
	    )
	  )
	  (net AND4_OUT
	    (joined
	      (portRef D
		(instanceRef C2AND2_OUT_reg)
	      )
	      (portRef D
		(instanceRef C2A_OUT_reg)
	      )
	      (portRef O
		(instanceRef C18)
	      )
	    )
	  )
	  (net Q0_OUT
	    (joined
	      (portRef Q
		(instanceRef Q0_OUT_reg)
	      )
	      (portRef I0
		(instanceRef C18)
	      )
	      (portRef I0
		(instanceRef C19)
	      )
	    )
	  )
	  (net Q1_OUT
	    (joined
	      (portRef Q
		(instanceRef Q1_OUT_reg)
	      )
	      (portRef I1
		(instanceRef C18)
	      )
	      (portRef I1
		(instanceRef C19)
	      )
	    )
	  )
	  (net Q2_OUT
	    (joined
	      (portRef Q
		(instanceRef Q2_OUT_reg)
	      )
	      (portRef I2
		(instanceRef C18)
	      )
	      (portRef I2
		(instanceRef C19)
	      )
	    )
	  )
	)
      )
    )
  )
  (design module_c
    (cellRef module_c
      (libraryRef DESIGNS)
    )
    (property PART
      (string "2V40CS144-5")
    )
  )
)