anal.info

一个简单的Modular Design设计,源代码

file {
  .version = 1;
  entity {
    .name = "module_c";
    .mra_file = "module_c.mra";
    .arch = {"verilog"};
    .syn_files = {"module_c%verilog.syn", "module_c%verilog__verilog.syn"};
   }
}