tb_wteam.vhd

简单的testbench制作方法

----------------------------------------------------
-- Library
----------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;
use IEEE.std_logic_unsigned.all ;

----------------------------------------------------
-- entity
----------------------------------------------------
entity tb_wteam is
end tb_wteam;

----------------------------------------------------
-- Architecture
----------------------------------------------------

architecture TB of tb_wteam is

  signal rst_clk             : std_logic := '0';                 -- test clock
  signal test_clk            : std_logic := '0';                 -- test clock
  signal guest_en            : std_logic := '0';                 -- 
  signal sevice_en           : std_logic := '0';                 -- 
  signal sev_wd_cnt          : std_logic_vector(3 downto 0) := (others => '0'); --

component wteam
  port ( 
        RST        : in     std_logic;                     
        CLK        : in     std_logic;                     
        A          : in     std_logic;                     
        B          : in     std_logic_vector (3 downto 0); 
        CH         : out    std_logic_vector (3 downto 0);
        CL         : out    std_logic_vector (3 downto 0);
        DH         : out    std_logic_vector (3 downto 0);
        DL         : out    std_logic_vector (3 downto 0);
        FH         : out    std_logic_vector (3 downto 0);
        FL         : out    std_logic_vector (3 downto 0);
        E          : out    std_logic_vector (3 downto 0) 
  );

end component;


begin

----------------------------------------------------
-- reset clock
----------------------------------------------------
p_rst_clock : process

begin

rst_clk <= '0';
wait for 20 ns;
rst_clk <= '1';
wait;

end process;

----------------------------------------------------
-- test clock
----------------------------------------------------
p_test_clock : process

begin

test_clk <= '0';
wait for 50 ns;
test_clk <= '1';
wait for 50 ns;

end process;


----------------------------------------------------
-- guest en 
----------------------------------------------------
p_guest_en : process

begin

guest_en <= '0';
wait for 300 ns;
guest_en <= '1';
wait for 300 ns;

end process;

----------------------------------------------------
-- sevice window en 
----------------------------------------------------
p_sevice_en : process

begin

sevice_en <= '0';
wait for 1500 ns;
sevice_en <= '1';
wait for 1500 ns;

end process;

p_sev_wd_cnt : process (sevice_en)

begin

  if (sevice_en'event and sevice_en = '1') then
    if (sev_wd_cnt < 9) then
      sev_wd_cnt <= sev_wd_cnt + 1;
    else
      sev_wd_cnt <= (others => '0');
    end if;
  end if;
end process;


i_wteam : wteam
  port map(  
           RST        => rst_clk,
           CLK        => test_clk,
           A          => guest_en,
           B          => sev_wd_cnt,
           CH         => open,
           CL         => open,
           DH         => open,
           DL         => open,
           FH         => open,
           FL         => open,
           E          => open
  );

end TB;