信号发生器之一.txt

FPGA 信号发生器的程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY singt IS
PORT(
	 CLK:IN STD_LOGIC;
     DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
     CARRY_OUT1:OUT STD_LOGIC
			);
END;
ARCHITECTURE dacc OF singt IS
COMPONENT data_rom
PORT(
	 address:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	 inclock:IN STD_LOGIC;
		q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
     );
END COMPONENT;
SIGNAL Q1:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL data:STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL CARRY_OUT:STD_LOGIC;
BEGIN
	PROCESS(CLK)
	BEGIN
		IF CLK'EVENT AND CLK='1'THEN
            IF(data=399)THEN
                data<="0000000000";
  				CARRY_OUT<='1';
             ELSE
                data<=data+1;
                CARRY_OUT<='0';
             END IF;
        END IF;
    END PROCESS;
    PROCESS(CARRY_OUT)
    BEGIN
        IF CARRY_OUT'EVENT AND CARRY_OUT='1'THEN
           IF(Q1=255)THEN
              Q1<="00000000";
           ELSE
              Q1<=Q1+1;
           END IF;
        END IF;
    END PROCESS;
U1:data_rom PORT MAP(address=>Q1,q=>DOUT,inclock=>CARRY_OUT);
CARRY_OUT1<=CARRY_OUT;
END;