board.h

此文件为GPS源代码

/*H**************************************************************************
* NAME:         board.h         
*----------------------------------------------------------------------------
* PURPOSE:
* This file contains the demonstration board definition
*****************************************************************************/

#ifndef _BOARD_H_
#define _BOARD_H_


/*_____ I N C L U D E S ____________________________________________________*/
#include "regsnd1.h"

/*_____ M A C R O S ________________________________________________________*/


/*----- Board definition -----*/

/* BOARD VERSION */
#define VERSION         36                  /* Version */
#define GL_BUF_SIZE     100
//#define REFD
/* MCU TO FLASH HARDWARE CONNECTION
P2.0--->CLE
P2.1--->ALE
P2.2--->WP
P2.7--->CE
p1.6--->RB
P3.6--->WE
P3.7--->RE
P0 ---->DATA
*/

/***  Type definition ***/

typedef unsigned char      Byte;
typedef unsigned char      Uchar;
typedef unsigned int       Uint16;
typedef int                Int16;
typedef float              Float16;
typedef unsigned long int  Uint32;
typedef long int           Int32;
typedef unsigned char      Bool;


/***  General purpose defines ***/

#define FALSE   0
#define TRUE    1
#define KO      0
#define OK      1
#define OFF     0
#define ON      1
#define CLR     0
#define SET     1

#define LOW(U16)   ((Byte)U16)
#define HIGH(U16)  ((Byte)(U16>>8))

/* Nand Flash Driver */
#define NF_1X_512B            0
#define NF_2X_512B            1
#define NF_1X_2KB             2
#define NF_2X_2KB             3

#define NF_CONFIG             NF_1X_2KB    /* _1X_512B, _2X_512B, _1X_2KB or _2X_2KB */
#define NF_CAPACITY_AUTO_DETECT   FALSE
#define NF_FULL_CHIP_ERASE        TRUE

/* NAND Flash (NF extended version) */
#define NF_128
#define NF_IDLE_STATE_ADD         0xFC      /* memory selected 	*/
#define NF_ADD_LATCH_ENABLE_ADD   0x7E00    /* Address Latch Enable Address */
#define NF_CMD_LATCH_ENABLE_ADD   0x7D00    /* Command Latch Enable Address */
#define NF_ADDRESS_CMD_DATA       0x7C00    /* Command / Data Address register */

#define NF_RD_BUSY                P1_6		
/* The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status  Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. (The Detail in k9f1028->40)*/
#define Nf_CS_ON()                (P2_7 = 0)
#define Nf_CS_OFF()               (P2_7= 1)
#define FLASH_WP        P2_2

/* define pins alias */
//#define CLE P2_0		//Command Latch Enable
//#define ALE P2_1		//Address Latch Enable
#define CE	P2_7		//Chip Enable
//#define WE	P3_6		//Write Enable
//#define RE	P3_7		//Read Enable
#define WP	P2_2		//Write Protection

/*_____ D E F I N I T I O N ________________________________________________*/


/*_____ D E C L A R A T I O N ______________________________________________*/


#endif    /* _BOARD_H_ */