hdb3.txt

HDB3码的VHDL实现 共三个模块：插入V、插入B以及单双极性变换

library ieee; 
use ieee.std_logic_1164.all; 
entity xhdb3 IS 
port(codein:in std_logic; 
clk: in std_logic; 
clr: in std_logic; 
codeout:out std_logic_vector(1 downto 0)); 
end xhdb3; 
architecture behave of xhdb3 is 
signal cnt0: integer:=0; 
signal flag0:integer range 1 downto 0 :=0; 
signal flag1:integer range 1 downto 0 :=0; 
signal flag2:integer range 1 downto 0 :=1; 
signal flag3:integer range 1 downto 0 :=0; 
signal firstv:integer range 1 downto 0 :=0; 
signal codeoutv:std_logic_vector(2 downto 0); 
signal s0:std_logic_vector(4 downto 0):="00000"; 
signal codeoutb:std_logic_vector(2 downto 0); 
signal s1:std_logic_vector(4 downto 0):="00000"; 
signal clkb:std_logic; 
signal clkv:std_logic; 
signal clkout:std_logic; 
signal s2:std_logic_vector(4 downto 0):="00000"; 
signal s3:std_logic_vector(2 downto 0); 
component dff 
port ( d : in std_logic; 
clk : in std_logic; 
q : out std_logic ); 
end component; 

begin 
--? ?vclk:clkv<=clk after 10 ns; 
add_v:process(clk,clr) 
begin 
if clk'event and clk='1'  then 
if clk='1'  then 
codeoutv<="000"; 
cnt0<=0; 
else 
case codein is 
when '1' =>
cnt0<=0; 
if(flag0=0) then 
codeoutv<="110"; 
flag0<=1; 
else 
codeoutv<="010"; 
flag0<=0; 
end if; 
when '0' =>
if cnt0=3 then 
if firstv=0 then 
if flag0=0 then 
codeoutv<="011"; 
flag1<=0; 
else 
codeoutv<="111"; 
flag1<=1; 
end if; 
firstv<=1; 
else 
if flag1=0 then 
codeoutv<="111"; 
flag1<=1; 
flag0<=1; 
else 
codeoutv<="011"; 
flag1<=0; 
flag0<=0; 
end if; 
end if; 
cnt0<=0; 
else 
cnt0<=cnt0+1; 
codeoutv<="000"; 
end if; 
when others=> 
codeoutv<="000"; 
cnt0<=cnt0; 

end case; 
end if; 
end if; 
end process add_v; 
s0(0)<=codeoutv(0); 
s1(0)<=codeoutv(1); 
s2(0)<=codeoutv(2); 
ds21:dff port map(s2(0),clk,s2(1)); 
ds11:dff port map(s1(0),clk,s1(1)); 
ds01:dff port map(s0(0),clk,s0(1)); 
ds22:dff port map(s2(1),clk,s2(2)); 
ds12:dff port map(s1(1),clk,s1(2)); 
ds02:dff port map(s0(1),clk,s0(2)); 
ds23:dff port map(s2(2),clk,s2(3)); 
ds13:dff port map(s1(2),clk,s1(3)); 
ds03:dff port map(s0(2),clk,s0(3)); 

bclk:clkb<= not clk ; 
add_b:process(clkb) 
begin 
if clkb'event and clkb='1'  then 
case codeoutv is 
when "110"=> 
flag3<=1; 
s2(4)<=s2(3); 
s1(4)<=s1(3); 
s0(4)<=s0(3); 
when "010"=> 
flag3<=0; 
s2(4)<=s2(3); 
s1(4)<=s1(3); 
s0(4)<=s0(3); 
when "111"=> 
if flag3=0 then 
s2(4)<='1';
s1(4)<='0';
s0(4)<='1';
flag3<=1; 
else 
s2(4)<=s2(3); 
s1(4)<=s1(3); 
s0(4)<=s0(3); 
end if; 
flag2<=1; 
when "011"=> 
if flag3=0 then 
s2(4)<=s2(3); 
s1(4)<=s1(3); 
s0(4)<=s0(3); 
else 
s2(4)<='1'; 
s1(4)<='0';
s0(4)<='1';
flag3<=0; 
end if; 
flag2<=0; 
when others=> 
s2(4)<=s2(3); 
s1(4)<=s1(3); 
s0(4)<=s0(3); 
end case; 
codeoutb<=s2(4)&s1(4)&s0(4); 
end if; 
end process add_b; 

outclk:clkout<=clk after 5 ns; 
output:process(clkout) 
begin 
 if clkout'event and clkout='1'  then 
if codeoutb="000" then 
codeout<="00"; 
elsif codeoutb="001"or codeoutb="010" or codeoutb="011" then 
codeout<="01"; 
else 
codeout<="10"; 
end if; 
end if; 
end process output; 
end behave ;