cic00.dat

《数字信号处理的FPGA实现》所附代码全

-- --------------------------------------------------------
-- Program for the design of a CIC decimator.
-- --------------------------------------------------------
--      Input bit width      Bin  =     8
--      Output bit width     Bout =    10
--      Number of stages     S    =     3
--      Decimation factor    R    =    32
--      COMB delay           D    =     2
--      Frequency resolution DR   =    64
--      Passband freq. ratio P    =     8
-- --------------------------------------------------------
-- ----------------- Results of the Design ----------------
-- --------------------------------------------------------
-- -------- Computed bit width:
-- -------- Maximum bit growth over all stages      =    18 
-- -------- Maximum bit width including sign Bmax+1 =    26 
-- Stage   1 INTEGRATOR. Bit width :  26 
-- Stage   2 INTEGRATOR. Bit width :  21 
-- Stage   3 INTEGRATOR. Bit width :  16 
-- Stage   1 COMB.       Bit width :  14 
-- Stage   2 COMB.       Bit width :  13 
-- Stage   3 COMB.       Bit width :  12 
-- ------- Maximum aliasing component : 0.002135 = 53.41 dB
-- ------- Amplitude distortion       : 0.729769 =  2.74 dB