95direct.v

《数字信号处理的FPGA实现》所附代码全

// ------------------------------------------------
// Verilog STD 1364-1995 compiler directives
// ------------------------------------------------

// LRM 16.1, p. 219:
`celldefine         
`endcelldefine 

// LRM 16.2, p. 219:
`default_nettype

// LRM 16.3, p. 220:
`define
`undef

// LRM 16.4, p. 222:
`else
`ifdef
`endif

// LRM 16.5, p. 224:
`include

// LRM 16.6, p. 225:
`resetall

// LRM 16.7, p. 225:
`timescale

// LRM 16.8, p. 227:
`nounconnected_drive