mhz.v

《数字信号处理的FPGA实现》所附代码全

MaxPlus 10p2 Verilog timing results: Device = EPF10K70RC240-4
File ADD_1P.TAO:
clk      l20.Q   dffs0.Q           15.8ns    63.29MHz
File ADD_2P.TAO:
clk      l20.Q   dffs0.Q           15.8ns    63.29MHz
File ADD_3P.TAO:
clk      l70.Q  dffs7.Q            16.4ns    60.97MHz
File AMMOD.TAO:
clk      z20.Q     z38.Q           28.5ns    35.08MHz
File BFPROC.TAO:
clk      Bim7.Q    119.Q           70.9ns    14.10MHz
File CIC3R32.TAO:
clk      c2d22.Q    c324.Q         28.1ns    35.58MHz
File CIC3S32.TAO:
clk      c2d22.Q    c310.Q         23.6ns    42.37MHz
File CORDIC.TAO:
clk      x23.Q     y37.Q           26.9ns    37.17MHz
File DAFSM.TAO:
clk      x00.Q       p4.Q          17.9ns    55.86MHz
File DAPARA.TAO:
clk      x12.Q     :46.Q           29.8ns    33.55MHz
File DAROM.TAO:
clk      x00.Q     p2.Q            35.4ns    28.24MHz
File DASIGN.TAO:
clk      x10.Q       p4.Q          28.1ns    35.58MHz
File DB4LATTI.TAO:
clk    x_wait1.Q    sx_low13.Q     18.6ns    53.76MHz
File DB4POLY.TAO:
clk     state0.Q    x_odd2.Q       13.4ns    74.62MHz
File DIV_AEGP.TAO:
clk      t1.Q      t6.Q            68.5ns    14.59MHz
File DIV_RES.TAO:
clk      state1.Q    r2.Q          28.6ns    34.96MHz
File EXAMPLE.TAO:
clk      s7.Q      s7.Q            8.0ns     125.00MHz
File FIR6DLMS.TAO:
clk     |lpm_mult:mul_3|sign_ff.Q  42.7ns    23.41MHz
File FIR_GEN.TAO:
clk   single_input_node1.Q a218.Q  24.2ns    41.32MHz
File FIR_LMS.TAO:
clk      x02.Q     f17.Q          111.0ns   9.00MHz
File FIR_SRG.TAO:
clk      tap10.Q    :92.Q          57.3ns    17.45MHz
File FUN_TEXT.TAO:
clk      dffs0.Q    dffs31.Q      18.3ns    54.64MHz
File IIR.TAO:
clk      x1.Q      y14.Q          25.1ns    39.84MHz
File IIR_PAR.TAO:
clk     clk_div2.Q      y7.Q      40.6ns    24.63MHz
File IIR_PIPE.TAO:
clk      x1.Q      x313.Q         20.1ns    49.75MHz
File LFSR.TAO:
clk      ff2.Q     ff3~1.Q        22.0ns    45.45MHz
File LFSR6S3.TAO:
clk      ff4.Q     ff2~1.Q        22.8ns    43.85MHz
File MUL_SER.TAO:
clk      state1.Q    a_reg6.Q     25.3ns    39.52MHz
File RADER7.TAO:
clk      x3.Q      x11118.Q       41.9ns    23.86MHz