mhz.vhd

《数字信号处理的FPGA实现》所附代码全

MaxPlus 10p2 VHDL timing results: Device = EPF10K70RC240-4
File ADD_1P.TAO:
clk      l20.Q     dffs0.Q        15.8ns    63.29MHz
File ADD_2P.TAO:
clk      l20.Q     dffs0.Q        15.8ns    63.29MHz
File ADD_3P.TAO:
clk      l70.Q    dffs7.Q         16.4ns    60.97MHz
File AMMOD.TAO:
clk      z1_4~229.Q  z2_7~229.Q   35.1ns    28.49MHz
File BFPROC.TAO:
clk      Bim7.Q    60.Q           73.7ns    13.56MHz
File CIC3R32.TAO:
clk     i2d22.Q    c123.Q         25.0ns    40.00MHz
File CIC3S32.TAO:
clk      x1.Q      i025.Q         22.4ns    44.64MHz
File CORDIC.TAO:
clk      y0_2.Q    x1_7.Q         25.2ns    39.68MHz
File DAFSM.TAO:
clk    x10.Q       p2.Q           17.8ns    56.17MHz
File DAPARA.TAO:
clk      x02.Q     :8.Q           31.4ns    31.84MHz
File DAROM.TAO:
clk      x00.Q     p2.Q           35.7ns    28.01MHz
File DASIGN.TAO:
clk    x20.Q       p4.Q           29.9ns    33.44MHz
File DB4LATTI.TAO:
clk   x_wait1.Q    sx_low14.Q     22.1ns    45.24MHz
File DB4POLY.TAO:
clk   state~1.Q    x_even3.Q      12.7ns    78.74MHz
File DIV_AEGP.TAO:
clk      t5.Q      t2.Q           68.5ns    14.59MHz
File DIV_RES.TAO:
clk      state~3.Q    r13.Q       26.6ns    37.59MHz
File EXAMPLE.TAO:
clk      s7.Q      s7.Q           8.0ns     125.00MHz
File FIR6DLMS.TAO:
clk      level_result_node0_2.Q    sign_ff.Q     42.7ns    23.41MHz
File FIR_GEN.TAO:
clk  decoder_node3_0.Q  level_result_node0_10.Q  24.0ns    41.66MHz
File FIR_LMS.TAO:
clk      x0_2.Q    f1_7.Q         111.0ns   9.00MHz
File FIR_SRG.TAO:
clk      tap1_0.Q    :10.Q        57.3ns    17.45MHz
File FUN_TEXT.TAO:
clk     dffs0.Q    dffs31.Q       18.3ns    54.64MHz
File IIR.TAO:
clk      x5.Q      y14.Q          23.3ns    42.91MHz
File IIR_PAR.TAO:
clk    clk_div2.Q    y_wait3.Q    31.9ns    31.34MHz
File IIR_PIPE.TAO:
clk      x1.Q      x313.Q         20.1ns    49.75MHz
File LFSR.TAO:
clk      ff2.Q     ff3~1.Q        22.0ns    45.45MHz
File LFSR6S3.TAO:
clk      ff4.Q     ff2~1.Q        22.8ns    43.85MHz
File MUL_SER.TAO:
clk      count1.Q    p0.Q         24.3ns    41.15MHz
File RADER7.TAO:
clk      x2.Q      x11118.Q       43.4ns    23.04MHz