jiaoyan.vhd

使用VHDL硬件描述语言边写的奇偶校验程序和3-8译码电路程序

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY jiaoyan IS
       PORT(
            databus:          IN std_logic_vector(7 downto 0);
            even_num,odd_num: OUT std_logic
            );
END jiaoyan;
ARCHITECTURE behav OF jiaoyan  IS
BEGIN
    PROCESS(databus)
         VARIABLE tmp:std_logic;
    BEGIN 
         tmp:='0';
         FOR I IN 0 TO 7 loop
             tmp:=tmp XOR databus(i);
         END LOOP;
         odd_num<=tmp;
         even_num<=NOT tmp;
     END PROCESS;
 END behav;