plj.fit.summary

来自「数字测频器」· SUMMARY 代码 · 共 18 行

Fitter Status : Successful - Sun May 11 14:25:06 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : plj
Top-level Entity Name : plj
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Logic utilization : 1 %
    Combinational ALUTs : 168 / 12,480 ( 1 % )
    Dedicated logic registers : 110 / 12,480 ( < 1 % )
Total registers : 110
Total pins : 15 / 343 ( 4 % )
Total virtual pins : 0
Total block memory bits : 0 / 419,328 ( 0 % )
DSP block 9-bit elements : 0 / 96 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )