plj.tan.qmsg

数字测频器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "start register b3\[2\] register b6\[3\] 331.13 MHz 3.02 ns Internal " "Info: Clock \"start\" has Internal fmax of 331.13 MHz between source register \"b3\[2\]\" and destination register \"b6\[3\]\" (period= 3.02 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.840 ns + Longest register register " "Info: + Longest register to register delay is 2.840 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns b3\[2\] 1 REG LCFF_X23_Y14_N11 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X23_Y14_N11; Fanout = 9; REG Node = 'b3\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { b3[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.366 ns) 0.916 ns b5\[3\]~596 2 COMB LCCOMB_X27_Y14_N2 1 " "Info: 2: + IC(0.550 ns) + CELL(0.366 ns) = 0.916 ns; Loc. = LCCOMB_X27_Y14_N2; Fanout = 1; COMB Node = 'b5\[3\]~596'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.916 ns" { b3[2] b5[3]~596 } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.216 ns) + CELL(0.154 ns) 1.286 ns b5\[3\]~592 3 COMB LCCOMB_X27_Y14_N30 6 " "Info: 3: + IC(0.216 ns) + CELL(0.154 ns) = 1.286 ns; Loc. = LCCOMB_X27_Y14_N30; Fanout = 6; COMB Node = 'b5\[3\]~592'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.370 ns" { b5[3]~596 b5[3]~592 } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.216 ns) + CELL(0.053 ns) 1.555 ns b6\[3\]~571 4 COMB LCCOMB_X27_Y14_N4 5 " "Info: 4: + IC(0.216 ns) + CELL(0.053 ns) = 1.555 ns; Loc. = LCCOMB_X27_Y14_N4; Fanout = 5; COMB Node = 'b6\[3\]~571'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.269 ns" { b5[3]~592 b6[3]~571 } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.746 ns) 2.840 ns b6\[3\] 5 REG LCFF_X25_Y14_N29 8 " "Info: 5: + IC(0.539 ns) + CELL(0.746 ns) = 2.840 ns; Loc. = LCFF_X25_Y14_N29; Fanout = 8; REG Node = 'b6\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.285 ns" { b6[3]~571 b6[3] } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns ( 46.44 % ) " "Info: Total cell delay = 1.319 ns ( 46.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.521 ns ( 53.56 % ) " "Info: Total interconnect delay = 1.521 ns ( 53.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.840 ns" { b3[2] b5[3]~596 b5[3]~592 b6[3]~571 b6[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.840 ns" { b3[2] {} b5[3]~596 {} b5[3]~592 {} b6[3]~571 {} b6[3] {} } { 0.000ns 0.550ns 0.216ns 0.216ns 0.539ns } { 0.000ns 0.366ns 0.154ns 0.053ns 0.746ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.004 ns - Smallest " "Info: - Smallest clock skew is 0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "start destination 4.305 ns + Shortest register " "Info: + Shortest clock path from clock \"start\" to destination register is 4.305 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns start 1 CLK PIN_M21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 3; CLK Node = 'start'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.880 ns) + CELL(0.053 ns) 1.797 ns bclk 2 COMB LCCOMB_X1_Y12_N20 1 " "Info: 2: + IC(0.880 ns) + CELL(0.053 ns) = 1.797 ns; Loc. = LCCOMB_X1_Y12_N20; Fanout = 1; COMB Node = 'bclk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.933 ns" { start bclk } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.218 ns) + CELL(0.000 ns) 3.015 ns bclk~clkctrl 3 COMB CLKCTRL_G2 30 " "Info: 3: + IC(1.218 ns) + CELL(0.000 ns) = 3.015 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'bclk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.218 ns" { bclk bclk~clkctrl } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.618 ns) 4.305 ns b6\[3\] 4 REG LCFF_X25_Y14_N29 8 " "Info: 4: + IC(0.672 ns) + CELL(0.618 ns) = 4.305 ns; Loc. = LCFF_X25_Y14_N29; Fanout = 8; REG Node = 'b6\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.290 ns" { bclk~clkctrl b6[3] } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.535 ns ( 35.66 % ) " "Info: Total cell delay = 1.535 ns ( 35.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.770 ns ( 64.34 % ) " "Info: Total interconnect delay = 2.770 ns ( 64.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.305 ns" { start bclk bclk~clkctrl b6[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.305 ns" { start {} start~combout {} bclk {} bclk~clkctrl {} b6[3] {} } { 0.000ns 0.000ns 0.880ns 1.218ns 0.672ns } { 0.000ns 0.864ns 0.053ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "start source 4.301 ns - Longest register " "Info: - Longest clock path from clock \"start\" to source register is 4.301 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns start 1 CLK PIN_M21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 3; CLK Node = 'start'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.880 ns) + CELL(0.053 ns) 1.797 ns bclk 2 COMB LCCOMB_X1_Y12_N20 1 " "Info: 2: + IC(0.880 ns) + CELL(0.053 ns) = 1.797 ns; Loc. = LCCOMB_X1_Y12_N20; Fanout = 1; COMB Node = 'bclk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.933 ns" { start bclk } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.218 ns) + CELL(0.000 ns) 3.015 ns bclk~clkctrl 3 COMB CLKCTRL_G2 30 " "Info: 3: + IC(1.218 ns) + CELL(0.000 ns) = 3.015 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'bclk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.218 ns" { bclk bclk~clkctrl } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.668 ns) + CELL(0.618 ns) 4.301 ns b3\[2\] 4 REG LCFF_X23_Y14_N11 9 " "Info: 4: + IC(0.668 ns) + CELL(0.618 ns) = 4.301 ns; Loc. = LCFF_X23_Y14_N11; Fanout = 9; REG Node = 'b3\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.286 ns" { bclk~clkctrl b3[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.535 ns ( 35.69 % ) " "Info: Total cell delay = 1.535 ns ( 35.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.766 ns ( 64.31 % ) " "Info: Total interconnect delay = 2.766 ns ( 64.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.301 ns" { start bclk bclk~clkctrl b3[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.301 ns" { start {} start~combout {} bclk {} bclk~clkctrl {} b3[2] {} } { 0.000ns 0.000ns 0.880ns 1.218ns 0.668ns } { 0.000ns 0.864ns 0.053ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.305 ns" { start bclk bclk~clkctrl b6[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.305 ns" { start {} start~combout {} bclk {} bclk~clkctrl {} b6[3] {} } { 0.000ns 0.000ns 0.880ns 1.218ns 0.672ns } { 0.000ns 0.864ns 0.053ns 0.000ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.301 ns" { start bclk bclk~clkctrl b3[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.301 ns" { start {} start~combout {} bclk {} bclk~clkctrl {} b3[2] {} } { 0.000ns 0.000ns 0.880ns 1.218ns 0.668ns } { 0.000ns 0.864ns 0.053ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.840 ns" { b3[2] b5[3]~596 b5[3]~592 b6[3]~571 b6[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.840 ns" { b3[2] {} b5[3]~596 {} b5[3]~592 {} b6[3]~571 {} b6[3] {} } { 0.000ns 0.550ns 0.216ns 0.216ns 0.539ns } { 0.000ns 0.366ns 0.154ns 0.053ns 0.746ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.305 ns" { start bclk bclk~clkctrl b6[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.305 ns" { start {} start~combout {} bclk {} bclk~clkctrl {} b6[3] {} } { 0.000ns 0.000ns 0.880ns 1.218ns 0.672ns } { 0.000ns 0.864ns 0.053ns 0.000ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.301 ns" { start bclk bclk~clkctrl b3[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.301 ns" { start {} start~combout {} bclk {} bclk~clkctrl {} b3[2] {} } { 0.000ns 0.000ns 0.880ns 1.218ns 0.668ns } { 0.000ns 0.864ns 0.053ns 0.000ns 0.618ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register b3\[2\] register b6\[3\] 331.13 MHz 3.02 ns Internal " "Info: Clock \"clk1\" has Internal fmax of 331.13 MHz between source register \"b3\[2\]\" and destination register \"b6\[3\]\" (period= 3.02 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.840 ns + Longest register register " "Info: + Longest register to register delay is 2.840 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns b3\[2\] 1 REG LCFF_X23_Y14_N11 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X23_Y14_N11; Fanout = 9; REG Node = 'b3\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { b3[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.366 ns) 0.916 ns b5\[3\]~596 2 COMB LCCOMB_X27_Y14_N2 1 " "Info: 2: + IC(0.550 ns) + CELL(0.366 ns) = 0.916 ns; Loc. = LCCOMB_X27_Y14_N2; Fanout = 1; COMB Node = 'b5\[3\]~596'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.916 ns" { b3[2] b5[3]~596 } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.216 ns) + CELL(0.154 ns) 1.286 ns b5\[3\]~592 3 COMB LCCOMB_X27_Y14_N30 6 " "Info: 3: + IC(0.216 ns) + CELL(0.154 ns) = 1.286 ns; Loc. = LCCOMB_X27_Y14_N30; Fanout = 6; COMB Node = 'b5\[3\]~592'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.370 ns" { b5[3]~596 b5[3]~592 } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.216 ns) + CELL(0.053 ns) 1.555 ns b6\[3\]~571 4 COMB LCCOMB_X27_Y14_N4 5 " "Info: 4: + IC(0.216 ns) + CELL(0.053 ns) = 1.555 ns; Loc. = LCCOMB_X27_Y14_N4; Fanout = 5; COMB Node = 'b6\[3\]~571'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.269 ns" { b5[3]~592 b6[3]~571 } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.746 ns) 2.840 ns b6\[3\] 5 REG LCFF_X25_Y14_N29 8 " "Info: 5: + IC(0.539 ns) + CELL(0.746 ns) = 2.840 ns; Loc. = LCFF_X25_Y14_N29; Fanout = 8; REG Node = 'b6\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.285 ns" { b6[3]~571 b6[3] } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns ( 46.44 % ) " "Info: Total cell delay = 1.319 ns ( 46.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.521 ns ( 53.56 % ) " "Info: Total interconnect delay = 1.521 ns ( 53.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.840 ns" { b3[2] b5[3]~596 b5[3]~592 b6[3]~571 b6[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.840 ns" { b3[2] {} b5[3]~596 {} b5[3]~592 {} b6[3]~571 {} b6[3] {} } { 0.000ns 0.550ns 0.216ns 0.216ns 0.539ns } { 0.000ns 0.366ns 0.154ns 0.053ns 0.746ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.004 ns - Smallest " "Info: - Smallest clock skew is 0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 4.492 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 4.492 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns clk1 1 CLK PIN_M20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M20; Fanout = 1; CLK Node = 'clk1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.892 ns) + CELL(0.228 ns) 1.984 ns bclk 2 COMB LCCOMB_X1_Y12_N20 1 " "Info: 2: + IC(0.892 ns) + CELL(0.228 ns) = 1.984 ns; Loc. = LCCOMB_X1_Y12_N20; Fanout = 1; COMB Node = 'bclk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.120 ns" { clk1 bclk } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.218 ns) + CELL(0.000 ns) 3.202 ns bclk~clkctrl 3 COMB CLKCTRL_G2 30 " "Info: 3: + IC(1.218 ns) + CELL(0.000 ns) = 3.202 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'bclk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.218 ns" { bclk bclk~clkctrl } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.618 ns) 4.492 ns b6\[3\] 4 REG LCFF_X25_Y14_N29 8 " "Info: 4: + IC(0.672 ns) + CELL(0.618 ns) = 4.492 ns; Loc. = LCFF_X25_Y14_N29; Fanout = 8; REG Node = 'b6\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.290 ns" { bclk~clkctrl b6[3] } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.710 ns ( 38.07 % ) " "Info: Total cell delay = 1.710 ns ( 38.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.782 ns ( 61.93 % ) " "Info: Total interconnect delay = 2.782 ns ( 61.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.492 ns" { clk1 bclk bclk~clkctrl b6[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.492 ns" { clk1 {} clk1~combout {} bclk {} bclk~clkctrl {} b6[3] {} } { 0.000ns 0.000ns 0.892ns 1.218ns 0.672ns } { 0.000ns 0.864ns 0.228ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 4.488 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 4.488 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns clk1 1 CLK PIN_M20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M20; Fanout = 1; CLK Node = 'clk1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.892 ns) + CELL(0.228 ns) 1.984 ns bclk 2 COMB LCCOMB_X1_Y12_N20 1 " "Info: 2: + IC(0.892 ns) + CELL(0.228 ns) = 1.984 ns; Loc. = LCCOMB_X1_Y12_N20; Fanout = 1; COMB Node = 'bclk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.120 ns" { clk1 bclk } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.218 ns) + CELL(0.000 ns) 3.202 ns bclk~clkctrl 3 COMB CLKCTRL_G2 30 " "Info: 3: + IC(1.218 ns) + CELL(0.000 ns) = 3.202 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'bclk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.218 ns" { bclk bclk~clkctrl } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.668 ns) + CELL(0.618 ns) 4.488 ns b3\[2\] 4 REG LCFF_X23_Y14_N11 9 " "Info: 4: + IC(0.668 ns) + CELL(0.618 ns) = 4.488 ns; Loc. = LCFF_X23_Y14_N11; Fanout = 9; REG Node = 'b3\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.286 ns" { bclk~clkctrl b3[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.710 ns ( 38.10 % ) " "Info: Total cell delay = 1.710 ns ( 38.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.778 ns ( 61.90 % ) " "Info: Total interconnect delay = 2.778 ns ( 61.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.488 ns" { clk1 bclk bclk~clkctrl b3[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.488 ns" { clk1 {} clk1~combout {} bclk {} bclk~clkctrl {} b3[2] {} } { 0.000ns 0.000ns 0.892ns 1.218ns 0.668ns } { 0.000ns 0.864ns 0.228ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.492 ns" { clk1 bclk bclk~clkctrl b6[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.492 ns" { clk1 {} clk1~combout {} bclk {} bclk~clkctrl {} b6[3] {} } { 0.000ns 0.000ns 0.892ns 1.218ns 0.672ns } { 0.000ns 0.864ns 0.228ns 0.000ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.488 ns" { clk1 bclk bclk~clkctrl b3[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.488 ns" { clk1 {} clk1~combout {} bclk {} bclk~clkctrl {} b3[2] {} } { 0.000ns 0.000ns 0.892ns 1.218ns 0.668ns } { 0.000ns 0.864ns 0.228ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "plj.vhd" "" { Text "E:/数字测频器/数字测频器/plj.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.840 ns" { b3[2] b5[3]~596 b5[3]~592 b6[3]~571 b6[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.840 ns" { b3[2] {} b5[3]~596 {} b5[3]~592 {} b6[3]~571 {} b6[3] {} } { 0.000ns 0.550ns 0.216ns 0.216ns 0.539ns } { 0.000ns 0.366ns 0.154ns 0.053ns 0.746ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.492 ns" { clk1 bclk bclk~clkctrl b6[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.492 ns" { clk1 {} clk1~combout {} bclk {} bclk~clkctrl {} b6[3] {} } { 0.000ns 0.000ns 0.892ns 1.218ns 0.672ns } { 0.000ns 0.864ns 0.228ns 0.000ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.488 ns" { clk1 bclk bclk~clkctrl b3[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.488 ns" { clk1 {} clk1~combout {} bclk {} bclk~clkctrl {} b3[2] {} } { 0.000ns 0.000ns 0.892ns 1.218ns 0.668ns } { 0.000ns 0.864ns 0.228ns 0.000ns 0.618ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}