plj.vhd

数字测频器

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;

entity plj is 
  port ( 
       start: in std_logic ;
       clk: in std_logic ;
       clk1: in std_logic ;
       yy1: out std_logic_vector(7 downto 0);
       w1: out std_logic_vector(3 downto 0)
       ); 
end plj;


architecture behav of plj is
    signal b1,b2,b3,b4,b5,b6,b7:std_logic_vector(3 downto 0);
    signal bcd:std_logic_vector(3 downto 0);
    signal q:integer range 0 to 49999999;
    signal qq:integer range 0 to 49999999;
    signal en,bclk:std_logic;
    signal sss:std_logic_vector (3 downto 0);
    signal bcd0,bcd1,bcd2,bcd3:std_logic_vector(3 downto 0);


begin 

second :process(clk)

begin 
     if start='1' then q<=0;
     elsif clk'event and clk='1' then 
             if q<49999999 then q<=q+1;
             else q<=49999999 ;
             end if;
     end if;
     if q<49999999 and start='0' then en<='1';
     else en<='0';
     end if;
end process;


and2:process(en,clk)

begin bclk<=clk1 and en ;
end process;

com:process(start,bclk)
begin 

if start='1' then 
        b1<="0000";b2<="0000";b3<="0000";b4<="0000";b5<="0000";b6<="0000";b7<="0000";
elsif bclk'event and bclk='1' then 
   if b1="1001" then b1<="0000";
      if b2="1001" then b2<="0000";
        if b3="1001" then b3<="0000";
          if b4="1001" then b4<="0000";
            if b5="1001" then b5<="0000";
              if b6="1001" then b6<="0000";
                if b7="1001" then b7<="0000";
                else b7<=b7+1;
                end if;
              else b6<=b6+1;
              end if;
            else b5<=b5+1;
            end if;
          else b4<=b4+1;
          end if;
        else b3<=b3+1;
        end if;
      else b2<=b2+1;
      end if;
    else b1<=b1+1;
    end if;
end if;
end process ;


process(clk)
begin 
     if rising_edge(clk) then
         if en='0' then
             if b7>"0000" then bcd3<=b7;bcd2<=b6;bcd1<=b5;bcd0<=b4;sss<="1110"; 
             elsif b6>"0000" then bcd3<=b6;bcd2<=b5;bcd1<=b4;bcd0<=b3;sss<="1101"; 
             elsif b5>"0000" then bcd3<=b5;bcd2<=b4;bcd1<=b3;bcd0<=b2;sss<="1011"; 
             else bcd3<=b4;bcd2<=b3;bcd1<=b2;bcd0<=b1;sss<="1111";
             end if;
         end if;
     end if;
end process;

weixuan :process(clk)

begin 
   if clk'event and clk='1' then  
      if qq<99999 then qq<=qq+1;bcd<=bcd3; w1<="0111";
         if sss="0111" then yy1(0)<='0';
         else yy1(0)<='1';
         end if;
      elsif qq<199999 then qq<=qq+1;bcd<=bcd2; w1<="1011";
         if sss="1011" then yy1(0)<='0';
         else yy1(0)<='1';
         end if;
      elsif qq<299999 then qq<=qq+1;bcd<=bcd1; w1<="1101";
         if sss="1101" then yy1(0)<='0';
         else yy1(0)<='1';
         end if;
      elsif qq<399999 then qq<=qq+1;bcd<=bcd0; w1<="1110";
         if sss="1110" then yy1(0)<='0';
         else yy1(0)<='1';
         end if;
      else qq<=0;
      end if;
   end if;
end process;


m0: process(bcd)
begin
   case bcd is 
        when "0000"=>yy1(7 downto 1)<="0000001"; 
        when "0001"=>yy1(7 downto 1)<="1001111"; 
        when "0010"=>yy1(7 downto 1)<="0010010"; 
        when "0011"=>yy1(7 downto 1)<="0000110"; 
        when "0100"=>yy1(7 downto 1)<="1001100"; 
        when "0101"=>yy1(7 downto 1)<="0100100"; 
        when "0110"=>yy1(7 downto 1)<="1100000"; 
        when "0111"=>yy1(7 downto 1)<="0001111"; 
        when "1000"=>yy1(7 downto 1)<="0000000"; 
        when "1001"=>yy1(7 downto 1)<="0001100"; 
        when others=>yy1(7 downto 1)<="1111111"; 
    end case;
  end process;
end behav;