plj.map.summary

数字测频器

Analysis & Synthesis Status : Successful - Sun May 11 14:24:53 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : plj
Top-level Entity Name : plj
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 166
    Dedicated logic registers : 108
Total registers : 108
Total pins : 15
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0