📄 plj.fit.rpt
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Fitter report for plj
Sun May 11 14:25:06 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Netlist Optimizations
5. HardCopy II Device Resource Guide
6. Pin-Out File
7. Fitter Resource Usage Summary
8. Input Pins
9. Output Pins
10. I/O Bank Usage
11. All Package Pins
12. Output Pin Default Load For Reported TCO
13. Fitter Resource Utilization by Entity
14. Delay Chain Summary
15. Pad To Core Delay Chain Fanout
16. Control Signals
17. Global & Other Fast Signals
18. Non-Global High Fan-Out Signals
19. Interconnect Usage Summary
20. LAB Logic Elements
21. LAB-wide Signals
22. LAB Signals Sourced
23. LAB Signals Sourced Out
24. LAB Distinct Inputs
25. I/O Rules Summary
26. I/O Rules Details
27. I/O Rules Matrix
28. Fitter Device Options
29. Operating Settings and Conditions
30. Advanced Data - General
31. Advanced Data - Placement Preparation
32. Advanced Data - Placement
33. Advanced Data - Routing
34. Fitter Messages
35. Fitter Suppressed Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+------------------------------------------+
; Fitter Status ; Successful - Sun May 11 14:25:06 2008 ;
; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name ; plj ;
; Top-level Entity Name ; plj ;
; Family ; Stratix II ;
; Device ; EP2S15F484C3 ;
; Timing Models ; Final ;
; Logic utilization ; 1 % ;
; Combinational ALUTs ; 168 / 12,480 ( 1 % ) ;
; Dedicated logic registers ; 110 / 12,480 ( < 1 % ) ;
; Total registers ; 110 ;
; Total pins ; 15 / 343 ( 4 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 419,328 ( 0 % ) ;
; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;
; Total PLLs ; 0 / 6 ( 0 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
+-------------------------------+------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; AUTO ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Use smart compilation ; Off ; Off ;
; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Always Enable Input Buffers ; Off ; Off ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing ; Off ; Off ;
; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
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