as.v

来自「本人在初学时做的小小的程序,测试关联的用法,通过调试.可能有些帮助」· Verilog 代码 · 共 21 行

module as(Z,A,B,C,D,E,F,G,H,TEMP1,TEMP2);
input A,B,C,D,E,F,G,H;
output TEMP1,TEMP2,Z;
wire [7:0] TEMP1;
wire [11:0] TEMP2;
and x1(TEMP1[0],A,B);
or  x2(TEMP1[1],C,D);
//and x3(TEMP1[2],E,F);
//or  x4(TEMP1[3],G,H);
assign TEMP1[7:6]={TEMP1[0],TEMP1[1]};
endmodule


module ab(E,F,Z,G,H);
input F,E,Z;
output G,H;
wire NOT1,NOT2,NOT3,NOT4;
as CON1(E,F,NOT1,NOT2);
as CON2(.A(Z),.C(G),.B(NOT1),.C(H));
endmodule