uart_tx.vhd

这个是UART的控制器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY uart_tx IS
	PORT
	(
		bclk,reset_n		: IN	STD_LOGIC;
		txd					: out	std_logic;
		
		tx_fifo_empty		: in	std_logic;
		tx_fifo_data		: in	std_logic_vector(7 downto 0);
		tx_fifo_rdreq		: out	std_logic;
		tcnt16_out			: out	std_logic_vector(4 downto 0)
	);
END uart_tx;
ARCHITECTURE behave OF uart_tx IS
	constant FrameLen 	:	integer := 8;
	
	type tx_state is(tx_idle,tx_start,tx_wait,tx_shift,tx_stop);
	signal	state,next_state :  tx_state;
	
	signal tbitcnt	: integer range 8 downto 0;
	SIGNAL tx_data 	: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
--=========================================
process(bclk,reset_n)
begin
	if (reset_n = '0') then
		state <= tx_idle;
	elsif rising_edge(bclk) then
		state <= next_state;
	end if;
end process;

--===========================================
Main_FSM:
PROCESS (bclk,state,tx_fifo_empty,tx_data,tx_fifo_data,tbitcnt)
	variable	tcnt16  	: std_logic_vector(4 downto 0);
BEGIN
if falling_edge(bclk) then
	case state is
	when tx_idle =>
		tcnt16 := (others =>'0');
		tbitcnt <= 0;
		txd<='1';--add
		tx_fifo_rdreq <= '0';
		if tx_fifo_empty = '0' then
			next_state <= tx_start;
			tx_fifo_rdreq <= '1'; --prepare to read tx_fifo data;
		else
			next_state <= tx_idle;
		end if;
	when tx_start=>
		tx_fifo_rdreq <= '0';
		txd <= '0';   --start bit;
		if tcnt16 = "01110"  then --???
			next_state <= tx_shift;
			tbitcnt <= 0;
--			tcnt16 := (others =>'0');
		else
			next_state <= tx_start;
			if tcnt16 = "00000" then
				tx_data <= tx_fifo_data;  --the data will be send 
			end if;
		end if;
		tcnt16 :=  tcnt16 + 1;
	when tx_shift =>
		txd <= tx_data(tbitcnt);
		next_state <= tx_wait;
		tcnt16 := (others =>'0');
		tbitcnt <= tbitcnt + 1;
	when tx_wait =>
		if tcnt16 = 14 then
			if tbitcnt ="01000" then
				next_state <= tx_stop;
				tcnt16 := (others =>'0');
			else
				next_state <= tx_shift;
			end if;
		else
			next_state <= tx_wait;
		end if;
		tcnt16 := tcnt16 + 1;
	when tx_stop =>
		tcnt16 := tcnt16 + 1;
		txd <= '1'; --stop bit
		if tcnt16 = "01111" then
			next_state <= tx_idle;
		else
			next_state <= tx_stop;
		end if;

		
	end case;
	
	tcnt16_out <= tcnt16;
	
end if;
end process main_FSM;
END behave;