baud.vhd

来自「这个是UART的控制器」· VHDL 代码 · 共 40 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE	IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;	
ENTITY baud IS
	GENERIC
		(
			XTAL_CLK	:	integer := 50000000;	--12M main clock crystal 
			BAUD		:	integer	:= 9600;		--serial port communcation baud
			cw			:	integer := 11			--store the count frequent division 
		);
	PORT
	(
		clk		: IN	STD_LOGIC;
		reset_n	: IN	STD_LOGIC;
		bclk	: OUT	STD_LOGIC
	);
END baud;
ARCHITECTURE behave OF baud IS
	constant 	CLK_DIV_coef :	integer := XTAL_CLK/(BAUD*16*2);  --count the number of main clock or direct number!!
	SIGNAL 		clk_div	: STD_LOGIC_VECTOR(cw-1 downto 0);
	SIGNAL 		bclk_t  : STD_LOGIC;
BEGIN
PROCESS (clk,reset_n)
BEGIN
	if (reset_n = '0') then
		clk_div <= (others=>'0');
		bclk_t <= '0';
	elsif rising_edge(clk) then
		if(clk_div = (clk_div_coef -1)) then --this value can be modified to change frequence
			clk_div <= (others =>'0');
			bclk_t <= not bclk_t;
		else
			clk_div <= clk_div +1;
		end if;	
	end if;
END PROCESS ;
	bclk <= bclk_t;
END behave;