uart_rx.vhd

这个是UART的控制器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;
ENTITY uart_rx IS
	PORT
	(
		bclk			: in 	std_logic;
		rxd				: IN	STD_LOGIC;
		reset_n			: in	std_logic;	
		rx_byte_done	: out	std_logic;
		rcv_data		: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
		--sta:out std_logic_vector(2 downto 0);
		rcnt16_out 		: out 	STD_LOGIC_VECTOR(4 DOWNTO 0)
	);
END uart_rx;
ARCHITECTURE behave OF uart_rx IS
	constant FrameLen 	:	integer := 8;
	
	type rx_state is(rx_idle,rx_start,rx_wait,rx_sample,rx_stop);
	signal	state,next_state :  rx_state;
	
	signal	rbitcnt			: integer range 8 downto 0;
	signal	rcv_data_reg  	: std_logic_vector(7 downto 0);
	signal  rxd_reg 		: std_logic;		
BEGIN
--=========================================
process(bclk,reset_n)
begin
	if (reset_n = '0') then
		state <= rx_idle;
	elsif rising_edge(bclk) then
		state <= next_state;
	end if;
end process;
--===========================================
Main_FSM:
PROCESS (bclk,state,rxd_reg,rbitcnt,rcv_data_reg)
	variable  rcnt16  	: std_logic_vector(4 downto 0);	--integer range 15 downto 0;
BEGIN
	if falling_edge(bclk) then
		case state is
		when rx_idle =>
			rcnt16 := (others => '0');
			rbitcnt <= 0;
			rx_byte_done <= '0';
			rcv_data_reg <= rcv_data_reg;
			if rxd_reg = '0' then
				next_state <= rx_start;
			else
				next_state <= rx_idle;
			end if;
		when rx_start =>
			rcv_data_reg <= rcv_data_reg;
			rx_byte_done <= '0';
			rbitcnt <= 0;
			rcnt16 := rcnt16 + 1;
			if  rxd_reg = '1' then 		--perhaps occur glitch 
				next_state <= rx_idle;
			elsif rcnt16 = "01000" then	--8
				next_state <= rx_wait;
				rcnt16 := (others => '0');
			else
				next_state <= rx_start;
			end if;
		when rx_wait =>
			rx_byte_done <= '0';
			rcv_data_reg <= rcv_data_reg;
			if rcnt16 = "01110" then	--15
				if rbitcnt= 8 then
					next_state <= rx_stop;
					rx_byte_done <= '1';	  --this signal indicate that this have received one full byte data
					rcv_data <= rcv_data_reg; 
				else 
					next_state <= rx_sample;
				end if;
			else
				next_state <= rx_wait;
			end if;
			
			rcnt16 := rcnt16 + 1;
			
		when rx_sample =>
			rx_byte_done <= '0';
			rcv_data_reg <= rcv_data_reg;
			rcv_data_reg(rbitcnt) <= rxd_reg;  --rbitcnt 0-7
			rbitcnt <= rbitcnt + 1;
			rcnt16 := (others => '0');
			next_state <= rx_wait;
		when rx_stop =>			--don't detect the stop bit,jump to rx_idle
			rcnt16 := (others => '0');
			rcv_data_reg <= rcv_data_reg;
			rx_byte_done <= '0';
			next_state <= rx_idle;
		when others =>
			rcnt16 := (others => '0');
			rcv_data_reg <= rcv_data_reg;
			rx_byte_done <= '0';
			next_state <= rx_idle;
		end case;	
		--	sta<=CONV_STD_LOGIC_VECTOR(next_state,3);
			rcnt16_out <= rcnt16;
		
	end if;
END PROCESS Main_FSM;
--====================================================--
		rxd_reg <= rxd;

END behave;