📄 count.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT IS
PORT(CLK:IN STD_LOGIC;
CHANGE:IN STD_LOGIC;
SEC_CHA:IN STD_LOGIC;
MIN_CHA:IN STD_LOGIC;
HOU_CHA:IN STD_LOGIC;
COUNT_SEC0,COUNT_SEC1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUNT_MIN0,COUNT_MIN1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUNT_HOU0,COUNT_HOU1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COUNT;
ARCHITECTURE BEHAVIO OF COUNT IS
SIGNAL SEC0:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL SEC1:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL MIN0:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL MIN1:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL HOU0:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL HOU1:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
PROCESS(CHANGE,CLK,SEC_CHA,MIN_CHA,HOU_CHA)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF CHANGE='0'THEN
IF SEC0="1001"THEN
SEC0<="0000";
IF SEC1="0101"THEN
SEC1<="0000";
IF MIN0="1001"THEN
MIN0<="0000";
IF MIN1="0101"THEN
MIN1<="0000";
if hou1<"0010"then
IF HOU0="1001"THEN
HOU0<="0000";
HOU1<=HOU1+1;
ELSE HOU0<=HOU0+1;
end if;
elsif hou1="0010"then
if hou0="0011"then
hou0<="0000";hou1<="0000";
else hou0<=hou0+1;
END IF;
end if;
ELSE MIN1<=MIN1+1;
END IF;
ELSE MIN0<=MIN0+1;
END IF;
ELSE SEC1<=SEC1+1;
END IF;
ELSE SEC0<=SEC0+1;
END IF;
ELSIF CHANGE='1'THEN
IF SEC_CHA='1' THEN
IF SEC0="1001"THEN
SEC0<="0000";
IF SEC1="0101"THEN
SEC1<="0000";
ELSE SEC1<=SEC1+1;
END IF;
ELSE SEC0<=SEC0+1;
END IF;
ELSIF MIN_CHA='1' THEN
IF MIN0="1001"THEN
MIN0<="0000";
IF MIN1="0101"THEN
MIN1<="0000";
ELSE MIN1<=MIN1+1;
END IF;
ELSE MIN0<=MIN0+1;
END IF;
ELSIF HOU_CHA='1' THEN
if hou1<"0010"then
IF HOU0="1001"THEN
HOU0<="0000";
HOU1<=HOU1+1;
ELSE HOU0<=HOU0+1;
end if;
elsif hou1="0010"then
if hou0="0011"then
hou0<="0000";hou1<="0000";
else hou0<=hou0+1;
END IF;
end if;
END IF;
END IF;
END IF;
END PROCESS;
COUNT_SEC0<=SEC0;
COUNT_SEC1<=SEC1;
COUNT_MIN0<=MIN0;
COUNT_MIN1<=MIN1;
COUNT_HOU0<=HOU0;
COUNT_HOU1<=HOU1;
END BEHAVIO;
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