clk_div3.vhd

来自「实现一个能显示时,分,秒,可设置闹钟的电子种,数码管显示时间」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CLK_DIV3 IS
PORT(CLK_1000 :IN STD_LOGIC;
     CLK_1HZ  :OUT STD_LOGIC);
END CLK_DIV3;
ARCHITECTURE BEHAVIORAL OF CLK_DIV3 IS
  SIGNAL CLK :STD_LOGIC;
BEGIN
PROCESS(CLK_1000)
  VARIABLE COUNT:INTEGER RANGE 0 TO 499;
  BEGIN
  IF CLK_1000'EVENT AND CLK_1000='1' THEN
     IF COUNT=499 THEN
        COUNT:=0;
        CLK<=(NOT CLK);
     ELSE  COUNT:=COUNT+1;
     END IF;
  END IF;
END PROCESS;
CLK_1HZ<=CLK;
END BEHAVIORAL;