elc_clock.fit.qmsg

实现一个能显示时,分,秒,可设置闹钟的电子种,数码管显示时间

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 23 15:48:48 2007 " "Info: Processing started: Mon Jul 23 15:48:48 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off elc_clock -c elc_clock " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off elc_clock -c elc_clock" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "elc_clock EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"elc_clock\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CLK (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "elc_clock.bdf" "" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 296 0 168 312 "CLK" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "" { CLK } "NODE_NAME" } "" } } { "D:/altera/qdesigns51/elc_clock/elc_clock.fld" "" { Floorplan "D:/altera/qdesigns51/elc_clock/elc_clock.fld" "" "" { CLK } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK_DIV3:inst2\|CLK  " "Info: Automatically promoted node CLK_DIV3:inst2\|CLK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CLK_DIV3:inst2\|CLK~35 " "Info: Destination node CLK_DIV3:inst2\|CLK~35" {  } { { "CLK_DIV3.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd" 13 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK_DIV3:inst2\|CLK~35" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "" { CLK_DIV3:inst2|CLK~35 } "NODE_NAME" } "" } } { "D:/altera/qdesigns51/elc_clock/elc_clock.fld" "" { Floorplan "D:/altera/qdesigns51/elc_clock/elc_clock.fld" "" "" { CLK_DIV3:inst2|CLK~35 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "CLK_DIV3.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd" 13 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK_DIV3:inst2\|CLK" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "" { CLK_DIV3:inst2|CLK } "NODE_NAME" } "" } } { "D:/altera/qdesigns51/elc_clock/elc_clock.fld" "" { Floorplan "D:/altera/qdesigns51/elc_clock/elc_clock.fld" "" "" { CLK_DIV3:inst2|CLK } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK_DIV1:inst\|CLK  " "Info: Automatically promoted node CLK_DIV1:inst\|CLK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CLK_DIV1:inst\|CLK~27 " "Info: Destination node CLK_DIV1:inst\|CLK~27" {  } { { "CLK_DIV1.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV1.vhd" 13 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK_DIV1:inst\|CLK~27" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "" { CLK_DIV1:inst|CLK~27 } "NODE_NAME" } "" } } { "D:/altera/qdesigns51/elc_clock/elc_clock.fld" "" { Floorplan "D:/altera/qdesigns51/elc_clock/elc_clock.fld" "" "" { CLK_DIV1:inst|CLK~27 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "CLK_DIV1.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV1.vhd" 13 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK_DIV1:inst\|CLK" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "" { CLK_DIV1:inst|CLK } "NODE_NAME" } "" } } { "D:/altera/qdesigns51/elc_clock/elc_clock.fld" "" { Floorplan "D:/altera/qdesigns51/elc_clock/elc_clock.fld" "" "" { CLK_DIV1:inst|CLK } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK_DIV2:inst1\|CLK  " "Info: Automatically promoted node CLK_DIV2:inst1\|CLK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "CLK_DIV2:inst1\|CLK~35 " "Info: Destination node CLK_DIV2:inst1\|CLK~35" {  } { { "CLK_DIV2.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd" 13 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK_DIV2:inst1\|CLK~35" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "" { CLK_DIV2:inst1|CLK~35 } "NODE_NAME" } "" } } { "D:/altera/qdesigns51/elc_clock/elc_clock.fld" "" { Floorplan "D:/altera/qdesigns51/elc_clock/elc_clock.fld" "" "" { CLK_DIV2:inst1|CLK~35 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "CLK_DIV2.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd" 13 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK_DIV2:inst1\|CLK" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "" { CLK_DIV2:inst1|CLK } "NODE_NAME" } "" } } { "D:/altera/qdesigns51/elc_clock/elc_clock.fld" "" { Floorplan "D:/altera/qdesigns51/elc_clock/elc_clock.fld" "" "" { CLK_DIV2:inst1|CLK } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}