elc_clock.map.qmsg

实现一个能显示时,分,秒,可设置闹钟的电子种,数码管显示时间

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 1991-2005 Altera Corporation. All rights reserved. " "Info: Copyright (C) 1991-2005 Altera Corporation. All rights reserved." {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Altera Corporation's design tools, logic functions  " "Info: Your use of Altera Corporation's design tools, logic functions " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and its AMPP partner logic  " "Info: and other software and tools, and its AMPP partner logic " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files any of the foregoing  " "Info: functions, and any output files any of the foregoing " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any  " "Info: (including device programming or simulation files), and any " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject  " "Info: associated documentation or information are expressly subject " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Altera Program License  " "Info: to the terms and conditions of the Altera Program License " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, Altera MegaCore Function License  " "Info: Subscription Agreement, Altera MegaCore Function License " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "Agreement, or other applicable license agreement, including,  " "Info: Agreement, or other applicable license agreement, including, " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "without limitation, that your use is for the sole purpose of  " "Info: without limitation, that your use is for the sole purpose of " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "programming logic devices manufactured by Altera and sold by  " "Info: programming logic devices manufactured by Altera and sold by " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "Altera or its authorized distributors.  Please refer to the  " "Info: Altera or its authorized distributors.  Please refer to the " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "applicable agreement for further details. " "Info: applicable agreement for further details." {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 01 16:44:19 2007 " "Info: Processing started: Wed Aug 01 16:44:19 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map D:\\altera\\qdesigns51\\elc_clock\\elc_clock.qpf --simgen --simgen_parameter=SIMGEN_C_NETLIST=ON,SIMGEN_OPTIMIZATION=ALL -c elc_clock " "Info: Command: quartus_map D:\\altera\\qdesigns51\\elc_clock\\elc_clock.qpf --simgen --simgen_parameter=SIMGEN_C_NETLIST=ON,SIMGEN_OPTIMIZATION=ALL -c elc_clock" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "COUNT.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file COUNT.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 COUNT-BEHAVIO " "Info: Found design unit 1: COUNT-BEHAVIO" {  } { { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 COUNT " "Info: Found entity 1: COUNT" {  } { { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DECODER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DECODER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DECODER-BEHAVIORAL " "Info: Found design unit 1: DECODER-BEHAVIORAL" {  } { { "DECODER.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/DECODER.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DECODER " "Info: Found entity 1: DECODER" {  } { { "DECODER.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/DECODER.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CLK_DIV1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CLK_DIV1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CLK_DIV1-BEHAVIORAL " "Info: Found design unit 1: CLK_DIV1-BEHAVIORAL" {  } { { "CLK_DIV1.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV1.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CLK_DIV1 " "Info: Found entity 1: CLK_DIV1" {  } { { "CLK_DIV1.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV1.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CLK_DIV2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CLK_DIV2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CLK_DIV2-BEHAVIORAL " "Info: Found design unit 1: CLK_DIV2-BEHAVIORAL" {  } { { "CLK_DIV2.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CLK_DIV2 " "Info: Found entity 1: CLK_DIV2" {  } { { "CLK_DIV2.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CLK_DIV3.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CLK_DIV3.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CLK_DIV3-BEHAVIORAL " "Info: Found design unit 1: CLK_DIV3-BEHAVIORAL" {  } { { "CLK_DIV3.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CLK_DIV3 " "Info: Found entity 1: CLK_DIV3" {  } { { "CLK_DIV3.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "elc_clock.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file elc_clock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 elc_clock " "Info: Found entity 1: elc_clock" {  } { { "elc_clock.bdf" "" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "elc_clock " "Info: Elaborating entity \"elc_clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DECODER DECODER:inst12 " "Info: Elaborating entity \"DECODER\" for hierarchy \"DECODER:inst12\"" {  } { { "elc_clock.bdf" "inst12" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 384 968 1112 480 "inst12" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "COUNT COUNT:inst14 " "Info: Elaborating entity \"COUNT\" for hierarchy \"COUNT:inst14\"" {  } { { "elc_clock.bdf" "inst14" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 120 632 840 280 "inst14" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CLK_DIV3 CLK_DIV3:inst2 " "Info: Elaborating entity \"CLK_DIV3\" for hierarchy \"CLK_DIV3:inst2\"" {  } { { "elc_clock.bdf" "inst2" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 120 432 584 216 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CLK_DIV2 CLK_DIV2:inst1 " "Info: Elaborating entity \"CLK_DIV2\" for hierarchy \"CLK_DIV2:inst1\"" {  } { { "elc_clock.bdf" "inst1" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 120 272 416 216 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CLK_DIV1 CLK_DIV1:inst " "Info: Elaborating entity \"CLK_DIV1\" for hierarchy \"CLK_DIV1:inst\"" {  } { { "elc_clock.bdf" "inst" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 120 112 256 216 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IQSYN_SIMGEN_INFO_MSG" "" "Info: Generating sgate simulator netlist using Simgen" {  } {  } 0 0 "Generating sgate simulator netlist using Simgen" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 01 16:44:22 2007 " "Info: Processing ended: Wed Aug 01 16:44:22 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}