elc_clock.tan.qmsg

实现一个能显示时,分,秒,可设置闹钟的电子种,数码管显示时间

{ "Info" "ITDB_TH_RESULT" "COUNT:inst14\|HOU1\[2\] CHANGE CLK 6.889 ns register " "Info: th for register \"COUNT:inst14\|HOU1\[2\]\" (data pin = \"CHANGE\", clock pin = \"CLK\") is 6.889 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 10.061 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 10.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLK 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "" { CLK } "NODE_NAME" } "" } } { "elc_clock.bdf" "" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 296 0 168 312 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLK~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "elc_clock.bdf" "" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 296 0 168 312 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.045 ns) + CELL(0.787 ns) 2.939 ns CLK_DIV1:inst\|CLK 3 REG LCFF_X31_Y35_N1 2 " "Info: 3: + IC(1.045 ns) + CELL(0.787 ns) = 2.939 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 2; REG Node = 'CLK_DIV1:inst\|CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.832 ns" { CLK~clkctrl CLK_DIV1:inst|CLK } "NODE_NAME" } "" } } { "CLK_DIV1.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV1.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.733 ns) + CELL(0.000 ns) 3.672 ns CLK_DIV1:inst\|CLK~clkctrl 4 COMB CLKCTRL_G10 10 " "Info: 4: + IC(0.733 ns) + CELL(0.000 ns) = 3.672 ns; Loc. = CLKCTRL_G10; Fanout = 10; COMB Node = 'CLK_DIV1:inst\|CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.733 ns" { CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl } "NODE_NAME" } "" } } { "CLK_DIV1.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV1.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.787 ns) 5.473 ns CLK_DIV2:inst1\|CLK 5 REG LCFF_X1_Y18_N29 2 " "Info: 5: + IC(1.014 ns) + CELL(0.787 ns) = 5.473 ns; Loc. = LCFF_X1_Y18_N29; Fanout = 2; REG Node = 'CLK_DIV2:inst1\|CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.801 ns" { CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK } "NODE_NAME" } "" } } { "CLK_DIV2.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.000 ns) 6.099 ns CLK_DIV2:inst1\|CLK~clkctrl 6 COMB CLKCTRL_G1 10 " "Info: 6: + IC(0.626 ns) + CELL(0.000 ns) = 6.099 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'CLK_DIV2:inst1\|CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.626 ns" { CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl } "NODE_NAME" } "" } } { "CLK_DIV2.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.787 ns) 7.924 ns CLK_DIV3:inst2\|CLK 7 REG LCFF_X64_Y19_N7 2 " "Info: 7: + IC(1.038 ns) + CELL(0.787 ns) = 7.924 ns; Loc. = LCFF_X64_Y19_N7; Fanout = 2; REG Node = 'CLK_DIV3:inst2\|CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.825 ns" { CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK } "NODE_NAME" } "" } } { "CLK_DIV3.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.582 ns) + CELL(0.000 ns) 8.506 ns CLK_DIV3:inst2\|CLK~clkctrl 8 COMB CLKCTRL_G5 24 " "Info: 8: + IC(0.582 ns) + CELL(0.000 ns) = 8.506 ns; Loc. = CLKCTRL_G5; Fanout = 24; COMB Node = 'CLK_DIV3:inst2\|CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.582 ns" { CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl } "NODE_NAME" } "" } } { "CLK_DIV3.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.537 ns) 10.061 ns COUNT:inst14\|HOU1\[2\] 9 REG LCFF_X61_Y6_N5 12 " "Info: 9: + IC(1.018 ns) + CELL(0.537 ns) = 10.061 ns; Loc. = LCFF_X61_Y6_N5; Fanout = 12; REG Node = 'COUNT:inst14\|HOU1\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.555 ns" { CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|HOU1[2] } "NODE_NAME" } "" } } { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.887 ns ( 38.63 % ) " "Info: Total cell delay = 3.887 ns ( 38.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.174 ns ( 61.37 % ) " "Info: Total interconnect delay = 6.174 ns ( 61.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51