elc_clock.tan.qmsg

实现一个能显示时,分,秒,可设置闹钟的电子种,数码管显示时间

{ "Info" "ITDB_TSU_RESULT" "COUNT:inst14\|SEC0\[1\] SEC_CHA CLK -3.727 ns register " "Info: tsu for register \"COUNT:inst14\|SEC0\[1\]\" (data pin = \"SEC_CHA\", clock pin = \"CLK\") is -3.727 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.356 ns + Longest pin register " "Info: + Longest pin to register delay is 6.356 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns SEC_CHA 1 PIN PIN_N26 4 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N26; Fanout = 4; PIN Node = 'SEC_CHA'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "" { SEC_CHA } "NODE_NAME" } "" } } { "elc_clock.bdf" "" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 368 408 576 384 "SEC_CHA" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.109 ns) + CELL(0.438 ns) 3.536 ns COUNT:inst14\|SEC0\[3\]~182 2 COMB LCCOMB_X61_Y5_N10 5 " "Info: 2: + IC(2.109 ns) + CELL(0.438 ns) = 3.536 ns; Loc. = LCCOMB_X61_Y5_N10; Fanout = 5; COMB Node = 'COUNT:inst14\|SEC0\[3\]~182'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "2.547 ns" { SEC_CHA COUNT:inst14|SEC0[3]~182 } "NODE_NAME" } "" } } { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.160 ns) + CELL(0.660 ns) 6.356 ns COUNT:inst14\|SEC0\[1\] 3 REG LCFF_X35_Y5_N29 11 " "Info: 3: + IC(2.160 ns) + CELL(0.660 ns) = 6.356 ns; Loc. = LCFF_X35_Y5_N29; Fanout = 11; REG Node = 'COUNT:inst14\|SEC0\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "2.820 ns" { COUNT:inst14|SEC0[3]~182 COUNT:inst14|SEC0[1] } "NODE_NAME" } "" } } { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.087 ns ( 32.84 % ) " "Info: Total cell delay = 2.087 ns ( 32.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.269 ns ( 67.16 % ) " "Info: Total interconnect delay = 4.269 ns ( 67.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "6.356 ns" { SEC_CHA COUNT:inst14|SEC0[3]~182 COUNT:inst14|SEC0[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.356 ns" { SEC_CHA SEC_CHA~combout COUNT:inst14|SEC0[3]~182 COUNT:inst14|SEC0[1] } { 0.000ns 0.000ns 2.109ns 2.160ns } { 0.000ns 0.989ns 0.438ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 10.047 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 10.047 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLK 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "" { CLK } "NODE_NAME" } "" } } { "elc_clock.bdf" "" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 296 0 168 312 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLK~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "elc_clock.bdf" "" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 296 0 168 312 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.045 ns) + CELL(0.787 ns) 2.939 ns CLK_DIV1:inst\|CLK 3 REG LCFF_X31_Y35_N1 2 " "Info: 3: + IC(1.045 ns) + CELL(0.787 ns) = 2.939 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 2; REG Node = 'CLK_DIV1:inst\|CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.832 ns" { CLK~clkctrl CLK_DIV1:inst|CLK } "NODE_NAME" } "" } } { "CLK_DIV1.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV1.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.733 ns) + CELL(0.000 ns) 3.672 ns CLK_DIV1:inst\|CLK~clkctrl 4 COMB CLKCTRL_G10 10 " "Info: 4: + IC(0.733 ns) + CELL(0.000 ns) = 3.672 ns; Loc. = CLKCTRL_G10; Fanout = 10; COMB Node = 'CLK_DIV1:inst\|CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.733 ns" { CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl } "NODE_NAME" } "" } } { "CLK_DIV1.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV1.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.787 ns) 5.473 ns CLK_DIV2:inst1\|CLK 5 REG LCFF_X1_Y18_N29 2 " "Info: 5: + IC(1.014 ns) + CELL(0.787 ns) = 5.473 ns; Loc. = LCFF_X1_Y18_N29; Fanout = 2; REG Node = 'CLK_DIV2:inst1\|CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.801 ns" { CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK } "NODE_NAME" } "" } } { "CLK_DIV2.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.000 ns) 6.099 ns CLK_DIV2:inst1\|CLK~clkctrl 6 COMB CLKCTRL_G1 10 " "Info: 6: + IC(0.626 ns) + CELL(0.000 ns) = 6.099 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'CLK_DIV2:inst1\|CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.626 ns" { CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl } "NODE_NAME" } "" } } { "CLK_DIV2.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.787 ns) 7.924 ns CLK_DIV3:inst2\|CLK 7 REG LCFF_X64_Y19_N7 2 " "Info: 7: + IC(1.038 ns) + CELL(0.787 ns) = 7.924 ns; Loc. = LCFF_X64_Y19_N7; Fanout = 2; REG Node = 'CLK_DIV3:inst2\|CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.825 ns" { CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK } "NODE_NAME" } "" } } { "CLK_DIV3.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.582 ns) + CELL(0.000 ns) 8.506 ns CLK_DIV3:inst2\|CLK~clkctrl 8 COMB CLKCTRL_G5 24 " "Info: 8: + IC(0.582 ns) + CELL(0.000 ns) = 8.506 ns; Loc. = CLKCTRL_G5; Fanout = 24; COMB Node = 'CLK_DIV3:inst2\|CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.582 ns" { CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl } "NODE_NAME" } "" } } { "CLK_DIV3.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.004 ns) + CELL(0.537 ns) 10.047 ns COUNT:inst14\|SEC0\[1\] 9 REG LCFF_X35_Y5_N29 11 " "Info: 9: + IC(1.004 ns) + CELL(0.537 ns) = 10.047 ns; Loc. = LCFF_X35_Y5_N29; Fanout = 11; REG Node = 'COUNT:inst14\|SEC0\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.541 ns" { CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|SEC0[1] } "NODE_NAME" } "" } } { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.887 ns ( 38.69 % ) " "Info: Total cell delay = 3.887 ns ( 38.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.160 ns ( 61.31 % ) " "Info: Total interconnect delay = 6.160 ns ( 61.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "10.047 ns" { CLK CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|SEC0[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.047 ns" { CLK CLK~combout CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|SEC0[1] } { 0.000ns 0.000ns 0.118ns 1.045ns 0.733ns 1.014ns 0.626ns 1.038ns 0.582ns 1.004ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "6.356 ns" { SEC_CHA COUNT:inst14|SEC0[3]~182 COUNT:inst14|SEC0[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.356 ns" { SEC_CHA SEC_CHA~combout COUNT:inst14|SEC0[3]~182 COUNT:inst14|SEC0[1] } { 0.000ns 0.000ns 2.109ns 2.160ns } { 0.000ns 0.989ns 0.438ns 0.660ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "10.047 ns" { CLK CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|SEC0[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.047 ns" { CLK CLK~combout CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|SEC0[1] } { 0.000ns 0.000ns 0.118ns 1.045ns 0.733ns 1.014ns 0.626ns 1.038ns 0.582ns 1.004ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK HOU1\[5\] COUNT:inst14\|HOU1\[0\] 19.022 ns register " "Info: tco from clock \"CLK\" to destination pin \"HOU1\[5\]\" through register \"COUNT:inst14\|HOU1\[0\]\" is 19.022 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 10.061 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 10.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLK 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "" { CLK } "NODE_NAME" } "" } } { "elc_clock.bdf" "" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 296 0 168 312 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLK~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "elc_clock.bdf" "" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 296 0 168 312 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.045 ns) + CELL(0.787 ns) 2.939 ns CLK_DIV1:inst\|CLK 3 REG LCFF_X31_Y35_N1 2 " "Info: 3: + IC(1.045 ns) + CELL(0.787 ns) = 2.939 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 2; REG Node = 'CLK_DIV1:inst\|CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.832 ns" { CLK~clkctrl CLK_DIV1:inst|CLK } "NODE_NAME" } "" } } { "CLK_DIV1.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV1.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.733 ns) + CELL(0.000 ns) 3.672 ns CLK_DIV1:inst\|CLK~clkctrl 4 COMB CLKCTRL_G10 10 " "Info: 4: + IC(0.733 ns) + CELL(0.000 ns) = 3.672 ns; Loc. = CLKCTRL_G10; Fanout = 10; COMB Node = 'CLK_DIV1:inst\|CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.733 ns" { CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl } "NODE_NAME" } "" } } { "CLK_DIV1.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV1.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.787 ns) 5.473 ns CLK_DIV2:inst1\|CLK 5 REG LCFF_X1_Y18_N29 2 " "Info: 5: + IC(1.014 ns) + CELL(0.787 ns) = 5.473 ns; Loc. = LCFF_X1_Y18_N29; Fanout = 2; REG Node = 'CLK_DIV2:inst1\|CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.801 ns" { CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK } "NODE_NAME" } "" } } { "CLK_DIV2.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.000 ns) 6.099 ns CLK_DIV2:inst1\|CLK~clkctrl 6 COMB CLKCTRL_G1 10 " "Info: 6: + IC(0.626 ns) + CELL(0.000 ns) = 6.099 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'CLK_DIV2:inst1\|CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.626 ns" { CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl } "NODE_NAME" } "" } } { "CLK_DIV2.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.787 ns) 7.924 ns CLK_DIV3:inst2\|CLK 7 REG LCFF_X64_Y19_N7 2 " "Info: 7: + IC(1.038 ns) + CELL(0.787 ns) = 7.924 ns; Loc. = LCFF_X64_Y19_N7; Fanout = 2; REG Node = 'CLK_DIV3:inst2\|CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.825 ns" { CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK } "NODE_NAME" } "" } } { "CLK_DIV3.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.582 ns) + CELL(0.000 ns) 8.506 ns CLK_DIV3:inst2\|CLK~clkctrl 8 COMB CLKCTRL_G5 24 " "Info: 8: + IC(0.582 ns) + CELL(0.000 ns) = 8.506 ns; Loc. = CLKCTRL_G5; Fanout = 24; COMB Node = 'CLK_DIV3:inst2\|CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.582 ns" { CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl } "NODE_NAME" } "" } } { "CLK_DIV3.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.537 ns) 10.061 ns COUNT:inst14\|HOU1\[0\] 9 REG LCFF_X61_Y6_N9 11 " "Info: 9: + IC(1.018 ns) + CELL(0.537 ns) = 10.061 ns; Loc. = LCFF_X61_Y6_N9; Fanout = 11; REG Node = 'COUNT:inst14\|HOU1\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.555 ns" { CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|HOU1[0] } "NODE_NAME" } "" } } { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.887 ns ( 38.63 % ) " "Info: Total cell delay = 3.887 ns ( 38.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.174 ns ( 61.37 % ) " "Info: Total interconnect delay = 6.174 ns ( 61.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "10.061 ns" { CLK CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|HOU1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.061 ns" { CLK CLK~combout CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|HOU1[0] } { 0.000ns 0.000ns 0.118ns 1.045ns 0.733ns 1.014ns 0.626ns 1.038ns 0.582ns 1.018ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.711 ns + Longest register pin " "Info: + Longest register to pin delay is 8.711 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns COUNT:inst14\|HOU1\[0\] 1 REG LCFF_X61_Y6_N9 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X61_Y6_N9; Fanout = 11; REG Node = 'COUNT:inst14\|HOU1\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "" { COUNT:inst14|HOU1[0] } "NODE_NAME" } "" } } { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.452 ns) + CELL(0.150 ns) 4.602 ns DECODER:inst13\|Q3\[5\]~99 2 COMB LCCOMB_X12_Y12_N0 1 " "Info: 2: + IC(4.452 ns) + CELL(0.150 ns) = 4.602 ns; Loc. = LCCOMB_X12_Y12_N0; Fanout = 1; COMB Node = 'DECODER:inst13\|Q3\[5\]~99'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "4.602 ns" { COUNT:inst14|HOU1[0] DECODER:inst13|Q3[5]~99 } "NODE_NAME" } "" } } { "DECODER.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/DECODER.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.497 ns) + CELL(2.612 ns) 8.711 ns HOU1\[5\] 3 PIN PIN_R4 0 " "Info: 3: + IC(1.497 ns) + CELL(2.612 ns) = 8.711 ns; Loc. = PIN_R4; Fanout = 0; PIN Node = 'HOU1\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "4.109 ns" { DECODER:inst13|Q3[5]~99 HOU1[5] } "NODE_NAME" } "" } } { "elc_clock.bdf" "" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 504 1152 1328 520 "HOU1\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.762 ns ( 31.71 % ) " "Info: Total cell delay = 2.762 ns ( 31.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.949 ns ( 68.29 % ) " "Info: Total interconnect delay = 5.949 ns ( 68.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "8.711 ns" { COUNT:inst14|HOU1[0] DECODER:inst13|Q3[5]~99 HOU1[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.711 ns" { COUNT:inst14|HOU1[0] DECODER:inst13|Q3[5]~99 HOU1[5] } { 0.000ns 4.452ns 1.497ns } { 0.000ns 0.150ns 2.612ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "10.061 ns" { CLK CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|HOU1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.061 ns" { CLK CLK~combout CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|HOU1[0] } { 0.000ns 0.000ns 0.118ns 1.045ns 0.733ns 1.014ns 0.626ns 1.038ns 0.582ns 1.018ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "8.711 ns" { COUNT:inst14|HOU1[0] DECODER:inst13|Q3[5]~99 HOU1[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.711 ns" { COUNT:inst14|HOU1[0] DECODER:inst13|Q3[5]~99 HOU1[5] } { 0.000ns 4.452ns 1.497ns } { 0.000ns 0.150ns 2.612ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}