elc_clock.tan.qmsg

实现一个能显示时,分,秒,可设置闹钟的电子种,数码管显示时间

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLK_DIV1:inst\|CLK " "Info: Detected ripple clock \"CLK_DIV1:inst\|CLK\" as buffer" {  } { { "CLK_DIV1.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV1.vhd" 13 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK_DIV1:inst\|CLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CLK_DIV2:inst1\|CLK " "Info: Detected ripple clock \"CLK_DIV2:inst1\|CLK\" as buffer" {  } { { "CLK_DIV2.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd" 13 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK_DIV2:inst1\|CLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CLK_DIV3:inst2\|CLK " "Info: Detected ripple clock \"CLK_DIV3:inst2\|CLK\" as buffer" {  } { { "CLK_DIV3.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd" 13 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK_DIV3:inst2\|CLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register COUNT:inst14\|SEC0\[1\] register COUNT:inst14\|HOU0\[2\] 174.49 MHz 5.731 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 174.49 MHz between source register \"COUNT:inst14\|SEC0\[1\]\" and destination register \"COUNT:inst14\|HOU0\[2\]\" (period= 5.731 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.531 ns + Longest register register " "Info: + Longest register to register delay is 5.531 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns COUNT:inst14\|SEC0\[1\] 1 REG LCFF_X35_Y5_N29 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y5_N29; Fanout = 11; REG Node = 'COUNT:inst14\|SEC0\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "" { COUNT:inst14|SEC0[1] } "NODE_NAME" } "" } } { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.636 ns) + CELL(0.438 ns) 3.074 ns rtl~307 2 COMB LCCOMB_X61_Y6_N16 4 " "Info: 2: + IC(2.636 ns) + CELL(0.438 ns) = 3.074 ns; Loc. = LCCOMB_X61_Y6_N16; Fanout = 4; COMB Node = 'rtl~307'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "3.074 ns" { COUNT:inst14|SEC0[1] rtl~307 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.277 ns) + CELL(0.438 ns) 3.789 ns COUNT:inst14\|HOU0\[0\]~602 3 COMB LCCOMB_X61_Y6_N22 2 " "Info: 3: + IC(0.277 ns) + CELL(0.438 ns) = 3.789 ns; Loc. = LCCOMB_X61_Y6_N22; Fanout = 2; COMB Node = 'COUNT:inst14\|HOU0\[0\]~602'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.715 ns" { rtl~307 COUNT:inst14|HOU0[0]~602 } "NODE_NAME" } "" } } { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.263 ns) + CELL(0.385 ns) 4.437 ns COUNT:inst14\|HOU0\[0\]~603 4 COMB LCCOMB_X61_Y6_N24 4 " "Info: 4: + IC(0.263 ns) + CELL(0.385 ns) = 4.437 ns; Loc. = LCCOMB_X61_Y6_N24; Fanout = 4; COMB Node = 'COUNT:inst14\|HOU0\[0\]~603'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.648 ns" { COUNT:inst14|HOU0[0]~602 COUNT:inst14|HOU0[0]~603 } "NODE_NAME" } "" } } { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.660 ns) 5.531 ns COUNT:inst14\|HOU0\[2\] 5 REG LCFF_X60_Y6_N5 11 " "Info: 5: + IC(0.434 ns) + CELL(0.660 ns) = 5.531 ns; Loc. = LCFF_X60_Y6_N5; Fanout = 11; REG Node = 'COUNT:inst14\|HOU0\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.094 ns" { COUNT:inst14|HOU0[0]~603 COUNT:inst14|HOU0[2] } "NODE_NAME" } "" } } { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.921 ns ( 34.73 % ) " "Info: Total cell delay = 1.921 ns ( 34.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.610 ns ( 65.27 % ) " "Info: Total interconnect delay = 3.610 ns ( 65.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "5.531 ns" { COUNT:inst14|SEC0[1] rtl~307 COUNT:inst14|HOU0[0]~602 COUNT:inst14|HOU0[0]~603 COUNT:inst14|HOU0[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.531 ns" { COUNT:inst14|SEC0[1] rtl~307 COUNT:inst14|HOU0[0]~602 COUNT:inst14|HOU0[0]~603 COUNT:inst14|HOU0[2] } { 0.000ns 2.636ns 0.277ns 0.263ns 0.434ns } { 0.000ns 0.438ns 0.438ns 0.385ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.014 ns - Smallest " "Info: - Smallest clock skew is 0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 10.061 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 10.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLK 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "" { CLK } "NODE_NAME" } "" } } { "elc_clock.bdf" "" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 296 0 168 312 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLK~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "elc_clock.bdf" "" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 296 0 168 312 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.045 ns) + CELL(0.787 ns) 2.939 ns CLK_DIV1:inst\|CLK 3 REG LCFF_X31_Y35_N1 2 " "Info: 3: + IC(1.045 ns) + CELL(0.787 ns) = 2.939 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 2; REG Node = 'CLK_DIV1:inst\|CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.832 ns" { CLK~clkctrl CLK_DIV1:inst|CLK } "NODE_NAME" } "" } } { "CLK_DIV1.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV1.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.733 ns) + CELL(0.000 ns) 3.672 ns CLK_DIV1:inst\|CLK~clkctrl 4 COMB CLKCTRL_G10 10 " "Info: 4: + IC(0.733 ns) + CELL(0.000 ns) = 3.672 ns; Loc. = CLKCTRL_G10; Fanout = 10; COMB Node = 'CLK_DIV1:inst\|CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.733 ns" { CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl } "NODE_NAME" } "" } } { "CLK_DIV1.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV1.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.787 ns) 5.473 ns CLK_DIV2:inst1\|CLK 5 REG LCFF_X1_Y18_N29 2 " "Info: 5: + IC(1.014 ns) + CELL(0.787 ns) = 5.473 ns; Loc. = LCFF_X1_Y18_N29; Fanout = 2; REG Node = 'CLK_DIV2:inst1\|CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.801 ns" { CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK } "NODE_NAME" } "" } } { "CLK_DIV2.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.000 ns) 6.099 ns CLK_DIV2:inst1\|CLK~clkctrl 6 COMB CLKCTRL_G1 10 " "Info: 6: + IC(0.626 ns) + CELL(0.000 ns) = 6.099 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'CLK_DIV2:inst1\|CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.626 ns" { CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl } "NODE_NAME" } "" } } { "CLK_DIV2.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.787 ns) 7.924 ns CLK_DIV3:inst2\|CLK 7 REG LCFF_X64_Y19_N7 2 " "Info: 7: + IC(1.038 ns) + CELL(0.787 ns) = 7.924 ns; Loc. = LCFF_X64_Y19_N7; Fanout = 2; REG Node = 'CLK_DIV3:inst2\|CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.825 ns" { CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK } "NODE_NAME" } "" } } { "CLK_DIV3.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.582 ns) + CELL(0.000 ns) 8.506 ns CLK_DIV3:inst2\|CLK~clkctrl 8 COMB CLKCTRL_G5 24 " "Info: 8: + IC(0.582 ns) + CELL(0.000 ns) = 8.506 ns; Loc. = CLKCTRL_G5; Fanout = 24; COMB Node = 'CLK_DIV3:inst2\|CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.582 ns" { CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl } "NODE_NAME" } "" } } { "CLK_DIV3.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.537 ns) 10.061 ns COUNT:inst14\|HOU0\[2\] 9 REG LCFF_X60_Y6_N5 11 " "Info: 9: + IC(1.018 ns) + CELL(0.537 ns) = 10.061 ns; Loc. = LCFF_X60_Y6_N5; Fanout = 11; REG Node = 'COUNT:inst14\|HOU0\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.555 ns" { CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|HOU0[2] } "NODE_NAME" } "" } } { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.887 ns ( 38.63 % ) " "Info: Total cell delay = 3.887 ns ( 38.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.174 ns ( 61.37 % ) " "Info: Total interconnect delay = 6.174 ns ( 61.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "10.061 ns" { CLK CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|HOU0[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.061 ns" { CLK CLK~combout CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|HOU0[2] } { 0.000ns 0.000ns 0.118ns 1.045ns 0.733ns 1.014ns 0.626ns 1.038ns 0.582ns 1.018ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 10.047 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 10.047 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLK 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "" { CLK } "NODE_NAME" } "" } } { "elc_clock.bdf" "" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 296 0 168 312 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLK~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "elc_clock.bdf" "" { Schematic "D:/altera/qdesigns51/elc_clock/elc_clock.bdf" { { 296 0 168 312 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.045 ns) + CELL(0.787 ns) 2.939 ns CLK_DIV1:inst\|CLK 3 REG LCFF_X31_Y35_N1 2 " "Info: 3: + IC(1.045 ns) + CELL(0.787 ns) = 2.939 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 2; REG Node = 'CLK_DIV1:inst\|CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.832 ns" { CLK~clkctrl CLK_DIV1:inst|CLK } "NODE_NAME" } "" } } { "CLK_DIV1.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV1.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.733 ns) + CELL(0.000 ns) 3.672 ns CLK_DIV1:inst\|CLK~clkctrl 4 COMB CLKCTRL_G10 10 " "Info: 4: + IC(0.733 ns) + CELL(0.000 ns) = 3.672 ns; Loc. = CLKCTRL_G10; Fanout = 10; COMB Node = 'CLK_DIV1:inst\|CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.733 ns" { CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl } "NODE_NAME" } "" } } { "CLK_DIV1.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV1.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.787 ns) 5.473 ns CLK_DIV2:inst1\|CLK 5 REG LCFF_X1_Y18_N29 2 " "Info: 5: + IC(1.014 ns) + CELL(0.787 ns) = 5.473 ns; Loc. = LCFF_X1_Y18_N29; Fanout = 2; REG Node = 'CLK_DIV2:inst1\|CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.801 ns" { CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK } "NODE_NAME" } "" } } { "CLK_DIV2.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.000 ns) 6.099 ns CLK_DIV2:inst1\|CLK~clkctrl 6 COMB CLKCTRL_G1 10 " "Info: 6: + IC(0.626 ns) + CELL(0.000 ns) = 6.099 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'CLK_DIV2:inst1\|CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.626 ns" { CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl } "NODE_NAME" } "" } } { "CLK_DIV2.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.787 ns) 7.924 ns CLK_DIV3:inst2\|CLK 7 REG LCFF_X64_Y19_N7 2 " "Info: 7: + IC(1.038 ns) + CELL(0.787 ns) = 7.924 ns; Loc. = LCFF_X64_Y19_N7; Fanout = 2; REG Node = 'CLK_DIV3:inst2\|CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.825 ns" { CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK } "NODE_NAME" } "" } } { "CLK_DIV3.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.582 ns) + CELL(0.000 ns) 8.506 ns CLK_DIV3:inst2\|CLK~clkctrl 8 COMB CLKCTRL_G5 24 " "Info: 8: + IC(0.582 ns) + CELL(0.000 ns) = 8.506 ns; Loc. = CLKCTRL_G5; Fanout = 24; COMB Node = 'CLK_DIV3:inst2\|CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "0.582 ns" { CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl } "NODE_NAME" } "" } } { "CLK_DIV3.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.004 ns) + CELL(0.537 ns) 10.047 ns COUNT:inst14\|SEC0\[1\] 9 REG LCFF_X35_Y5_N29 11 " "Info: 9: + IC(1.004 ns) + CELL(0.537 ns) = 10.047 ns; Loc. = LCFF_X35_Y5_N29; Fanout = 11; REG Node = 'COUNT:inst14\|SEC0\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "1.541 ns" { CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|SEC0[1] } "NODE_NAME" } "" } } { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.887 ns ( 38.69 % ) " "Info: Total cell delay = 3.887 ns ( 38.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.160 ns ( 61.31 % ) " "Info: Total interconnect delay = 6.160 ns ( 61.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "10.047 ns" { CLK CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|SEC0[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.047 ns" { CLK CLK~combout CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|SEC0[1] } { 0.000ns 0.000ns 0.118ns 1.045ns 0.733ns 1.014ns 0.626ns 1.038ns 0.582ns 1.004ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "10.061 ns" { CLK CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|HOU0[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.061 ns" { CLK CLK~combout CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|HOU0[2] } { 0.000ns 0.000ns 0.118ns 1.045ns 0.733ns 1.014ns 0.626ns 1.038ns 0.582ns 1.018ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "10.047 ns" { CLK CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|SEC0[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.047 ns" { CLK CLK~combout CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|SEC0[1] } { 0.000ns 0.000ns 0.118ns 1.045ns 0.733ns 1.014ns 0.626ns 1.038ns 0.582ns 1.004ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "COUNT.vhd" "" { Text "D:/altera/qdesigns51/elc_clock/COUNT.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "5.531 ns" { COUNT:inst14|SEC0[1] rtl~307 COUNT:inst14|HOU0[0]~602 COUNT:inst14|HOU0[0]~603 COUNT:inst14|HOU0[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.531 ns" { COUNT:inst14|SEC0[1] rtl~307 COUNT:inst14|HOU0[0]~602 COUNT:inst14|HOU0[0]~603 COUNT:inst14|HOU0[2] } { 0.000ns 2.636ns 0.277ns 0.263ns 0.434ns } { 0.000ns 0.438ns 0.438ns 0.385ns 0.660ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "10.061 ns" { CLK CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|HOU0[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.061 ns" { CLK CLK~combout CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|HOU0[2] } { 0.000ns 0.000ns 0.118ns 1.045ns 0.733ns 1.014ns 0.626ns 1.038ns 0.582ns 1.018ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "elc_clock" "UNKNOWN" "V1" "D:/altera/qdesigns51/elc_clock/db/elc_clock.quartus_db" { Floorplan "D:/altera/qdesigns51/elc_clock/" "" "10.047 ns" { CLK CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|SEC0[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.047 ns" { CLK CLK~combout CLK~clkctrl CLK_DIV1:inst|CLK CLK_DIV1:inst|CLK~clkctrl CLK_DIV2:inst1|CLK CLK_DIV2:inst1|CLK~clkctrl CLK_DIV3:inst2|CLK CLK_DIV3:inst2|CLK~clkctrl COUNT:inst14|SEC0[1] } { 0.000ns 0.000ns 0.118ns 1.045ns 0.733ns 1.014ns 0.626ns 1.038ns 0.582ns 1.004ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}