clk_div1.vhd

来自「实现一个能显示时,分,秒,可设置闹钟的电子种,数码管显示时间」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CLK_DIV1 IS
PORT(CLK_50M :IN STD_LOGIC;
     CLK_1M  :OUT STD_LOGIC);
END CLK_DIV1;
ARCHITECTURE BEHAVIORAL OF CLK_DIV1 IS
  SIGNAL CLK :STD_LOGIC;
BEGIN
PROCESS(CLK_50M)
  VARIABLE COUNT:INTEGER RANGE 0 TO 24;
  BEGIN
  IF CLK_50M'EVENT AND CLK_50M='1' THEN
     IF COUNT=24 THEN
        COUNT:=0;
        CLK<=(NOT CLK);
     ELSE  COUNT:=COUNT+1;
     END IF;
  END IF;
END PROCESS;
CLK_1M<=CLK;
END BEHAVIORAL;