📄 elc_clock.bdf
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "CLK" (rect 5 0 26 12)(font "Arial" ))
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(annotation_block (location)(rect 1328 520 1416 632))
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(symbol
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(text "CLK_DIV1" (rect 5 0 56 12)(font "Arial" ))
(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "CLK_50M" (rect 0 0 47 12)(font "Arial" ))
(text "CLK_50M" (rect 21 27 68 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
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(output)
(text "CLK_1M" (rect 0 0 41 12)(font "Arial" ))
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(line (pt 144 32)(pt 128 32)(line_width 1))
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(drawing
(rectangle (rect 16 16 128 80)(line_width 1))
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(port
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(port
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(line (pt 144 32)(pt 128 32)(line_width 1))
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(symbol
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(text "CLK_DIV3" (rect 5 0 56 12)(font "Arial" ))
(text "inst2" (rect 8 80 31 92)(font "Arial" ))
(port
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(text "CLK_1000" (rect 21 27 71 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
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(text "CLK_1HZ" (rect 83 27 131 39)(font "Arial" ))
(line (pt 152 32)(pt 136 32)(line_width 1))
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(drawing
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(port
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