clk_div2.vhd

实现一个能显示时,分,秒,可设置闹钟的电子种,数码管显示时间

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CLK_DIV2 IS
PORT(CLK_1M :IN STD_LOGIC;
     CLK_1000  :OUT STD_LOGIC);
END CLK_DIV2;
ARCHITECTURE BEHAVIORAL OF CLK_DIV2 IS
  SIGNAL CLK :STD_LOGIC;
BEGIN
PROCESS(CLK_1M)
  VARIABLE COUNT:INTEGER RANGE 0 TO 499;
  BEGIN
  IF CLK_1M'EVENT AND CLK_1M='1' THEN
     IF COUNT=499 THEN
        COUNT:=0;
        CLK<=(NOT CLK);
     ELSE  COUNT:=COUNT+1;
     END IF;
  END IF;
END PROCESS;
CLK_1000<=CLK;
END BEHAVIORAL;