📄 elc_clock.map.rpt
字号:
; CLK_DIV2.vhd ; yes ; User VHDL File ; D:/altera/qdesigns51/elc_clock/CLK_DIV2.vhd ;
; CLK_DIV3.vhd ; yes ; User VHDL File ; D:/altera/qdesigns51/elc_clock/CLK_DIV3.vhd ;
; elc_clock.bdf ; yes ; User Block Diagram/Schematic File ; D:/altera/qdesigns51/elc_clock/elc_clock.bdf ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------+
+------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+--------------------+
; Resource ; Usage ;
+---------------------------------------------+--------------------+
; Total combinational functions ; 138 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 90 ;
; -- 3 input functions ; 14 ;
; -- <=2 input functions ; 34 ;
; -- Combinational cells for routing ; 0 ;
; Logic elements by mode ; ;
; -- normal mode ; 115 ;
; -- arithmetic mode ; 23 ;
; Total registers ; 50 ;
; I/O pins ; 47 ;
; Maximum fan-out node ; CLK_DIV3:inst2|CLK ;
; Maximum fan-out ; 25 ;
; Total fan-out ; 619 ;
; Average fan-out ; 2.63 ;
+---------------------------------------------+--------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+
; |elc_clock ; 138 (10) ; 50 (0) ; 0 ; 0 ; 0 ; 0 ; 47 ; 0 ; |elc_clock ;
; |CLK_DIV1:inst| ; 9 (9) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |elc_clock|CLK_DIV1:inst ;
; |CLK_DIV2:inst1| ; 16 (16) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |elc_clock|CLK_DIV2:inst1 ;
; |CLK_DIV3:inst2| ; 16 (16) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |elc_clock|CLK_DIV3:inst2 ;
; |COUNT:inst14| ; 45 (45) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |elc_clock|COUNT:inst14 ;
; |DECODER:inst10| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |elc_clock|DECODER:inst10 ;
; |DECODER:inst11| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |elc_clock|DECODER:inst11 ;
; |DECODER:inst12| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |elc_clock|DECODER:inst12 ;
; |DECODER:inst13| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |elc_clock|DECODER:inst13 ;
; |DECODER:inst8| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |elc_clock|DECODER:inst8 ;
; |DECODER:inst9| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |elc_clock|DECODER:inst9 ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 50 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 16 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |elc_clock|COUNT:inst14|SEC0[3] ;
; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |elc_clock|COUNT:inst14|SEC1[0] ;
; 6:1 ; 4 bits ; 16 LEs ; 4 LEs ; 12 LEs ; Yes ; |elc_clock|COUNT:inst14|MIN0[3] ;
; 7:1 ; 4 bits ; 16 LEs ; 4 LEs ; 12 LEs ; Yes ; |elc_clock|COUNT:inst14|MIN1[3] ;
; 11:1 ; 4 bits ; 28 LEs ; 4 LEs ; 24 LEs ; Yes ; |elc_clock|COUNT:inst14|HOU1[0] ;
; 12:1 ; 4 bits ; 32 LEs ; 4 LEs ; 28 LEs ; Yes ; |elc_clock|COUNT:inst14|HOU0[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/altera/qdesigns51/elc_clock/elc_clock.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Mon Jul 23 15:48:43 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off elc_clock -c elc_clock
Info: Found 2 design units, including 1 entities, in source file COUNT.vhd
Info: Found design unit 1: COUNT-BEHAVIO
Info: Found entity 1: COUNT
Info: Found 2 design units, including 1 entities, in source file DECODER.vhd
Info: Found design unit 1: DECODER-BEHAVIORAL
Info: Found entity 1: DECODER
Info: Found 2 design units, including 1 entities, in source file CLK_DIV1.vhd
Info: Found design unit 1: CLK_DIV1-BEHAVIORAL
Info: Found entity 1: CLK_DIV1
Info: Found 2 design units, including 1 entities, in source file CLK_DIV2.vhd
Info: Found design unit 1: CLK_DIV2-BEHAVIORAL
Info: Found entity 1: CLK_DIV2
Info: Found 2 design units, including 1 entities, in source file CLK_DIV3.vhd
Info: Found design unit 1: CLK_DIV3-BEHAVIORAL
Info: Found entity 1: CLK_DIV3
Info: Found 1 design units, including 1 entities, in source file elc_clock.bdf
Info: Found entity 1: elc_clock
Info: Elaborating entity "elc_clock" for the top level hierarchy
Info: Elaborating entity "DECODER" for hierarchy "DECODER:inst12"
Info: Elaborating entity "COUNT" for hierarchy "COUNT:inst14"
Info: Elaborating entity "CLK_DIV3" for hierarchy "CLK_DIV3:inst2"
Info: Elaborating entity "CLK_DIV2" for hierarchy "CLK_DIV2:inst1"
Info: Elaborating entity "CLK_DIV1" for hierarchy "CLK_DIV1:inst"
Info: Implemented 185 device resources after synthesis - the final resource count might be different
Info: Implemented 5 input pins
Info: Implemented 42 output pins
Info: Implemented 138 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Processing ended: Mon Jul 23 15:48:46 2007
Info: Elapsed time: 00:00:04
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -