📄 serial.txt
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity chuankou is
port(
clk:in std_logic; --时钟信号
con:out std_logic; --控制信号
equal:buffer std_logic; --检测输出信号
z:out std_logic; --信号发生器的输出
q:out std_logic_vector(6 downto 0)); --并行输出信号
end;
architecture behavior of chuankou is
signal temp,temp1:std_logic:='0';
signal temp4:std_logic:='0'; --控制电路输出信号
signal temp2: std_logic_vector(6 downto 0):="0000000";
signal temp3: std_logic_vector(6 downto 0):="0000000";
signal temp5: std_logic_vector(6 downto 0):="0000000";
begin
pro1: process(clk) --函数信号发生器
variable count: integer range 0 to 14; --计数器
begin
if(clk'event and clk='1')then --根据要产生的信号分配输出电平的高低
if count=0 then
temp<='1';
count:=count+1;
elsif(count<4)then --4个1
temp<='1';
count:=count+1;
elsif(count>3 and count<7)then --3个0
temp<='0';
count:=count+1;
elsif(count>6 and count<8)then --1个1
temp<='1';
count:=count+1;
elsif(count>7 and count<10)then --2个0
temp<='0';
count:=count+1;
elsif(count>9 and count<12)then --2个1
temp<='1';
count:=count+1;
elsif(count=12)then --1个0
temp<='0';
count:=count+1;
elsif(count=13)then --1个1
temp<='1';
count:=count+1;
elsif(count=14)then --1个0
temp<='0';
count:=0; --循环结束
end if;
end if;
temp1<=temp;
end process;
z<=temp1;
pro2: process(clk) --串并转换
begin
if(clk'event and clk='1')then
temp2(6)<=temp2(5);
temp2(5)<=temp2(4);
temp2(4)<=temp2(3);
temp2(3)<=temp2(2);
temp2(2)<=temp2(1);
temp2(1)<=temp2(0);
temp2(0)<=temp1;
end if;
end process;
temp3<=temp2;
pro3:process(clk) --检测电路
begin
if (temp3="1111000")then
equal<='1';
else equal<='0';
end if;
end process;
pro4:process(equal) --控制电路
begin
if(equal'event and equal='1')then
temp4<='1';
end if;
end process;
con<=temp4;
pro5: process(clk) --锁存输出
begin
if(clk'event and clk='1')then
if(temp4='1')then
temp5<=temp3;
else temp5<="0000000";
end if;
end if;
end process;
q<=temp5;
end;
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