rt_rt2500pci.c

硬实时linux补丁rtai下的网络协议栈 最新

    rt2x00_register_read(rt2x00pci, RXCSR3, &reg);
    rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47);		/* Signal. */
    rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
    rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51);		/* Rssi. */
    rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
    rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42);		/* OFDM Rate. */
    rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
    rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51);		/* OFDM. */
    rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
    rt2x00_register_write(rt2x00pci, RXCSR3, reg);

    rt2x00_register_read(rt2x00pci, RALINKCSR, &reg);
    rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
    rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
    rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
    rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
    rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
    rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
    rt2x00_register_write(rt2x00pci, RALINKCSR, reg);

    rt2x00_register_write(rt2x00pci, BBPCSR1, cpu_to_le32(0x82188200));

    rt2x00_register_write(rt2x00pci, TXACKCSR0, cpu_to_le32(0x00000020));

    rt2x00_register_write(rt2x00pci, ARTCSR0, cpu_to_le32(0x7038140a));
    rt2x00_register_write(rt2x00pci, ARTCSR1, cpu_to_le32(0x1d21252d));
    rt2x00_register_write(rt2x00pci, ARTCSR2, cpu_to_le32(0x1919191d));

    /* disable Beacon timer */
    rt2x00_register_write(rt2x00pci, CSR14, 0x0);

    reg = 0x00000000;
    rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 30);
    rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 70);
    rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
    rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
    rt2x00_register_write(rt2x00pci, LEDCSR, reg);

    reg = 0x00000000;
    rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
    rt2x00_register_write(rt2x00pci, CSR1, reg);

    reg = 0x00000000;
    rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
    rt2x00_register_write(rt2x00pci, CSR1, reg);

    /*
     * We must clear the FCS and FIFI error count.
     * These registers are cleared on read, so we may pass a useless variable to store the value.
     */
    rt2x00_register_read(rt2x00pci, CNT0, &reg);
    rt2x00_register_read(rt2x00pci, CNT4, &reg);

    return 0;
}

static void
rt2x00_init_write_mac(struct _rt2x00_pci *rt2x00pci, struct rtnet_device *rtnet_dev) {

    u32			reg[2];

    memset(&reg, 0x00, sizeof(reg));

    rt2x00_set_field32(&reg[0], CSR3_BYTE0, rtnet_dev->dev_addr[0]);
    rt2x00_set_field32(&reg[0], CSR3_BYTE1, rtnet_dev->dev_addr[1]);
    rt2x00_set_field32(&reg[0], CSR3_BYTE2, rtnet_dev->dev_addr[2]);
    rt2x00_set_field32(&reg[0], CSR3_BYTE3, rtnet_dev->dev_addr[3]);
    rt2x00_set_field32(&reg[1], CSR4_BYTE4, rtnet_dev->dev_addr[4]);
    rt2x00_set_field32(&reg[1], CSR4_BYTE5, rtnet_dev->dev_addr[5]);

    rt2x00_register_multiwrite(rt2x00pci, CSR3, &reg[0], sizeof(reg));
}


static int
rt2x00_init_bbp(struct _rt2x00_pci *rt2x00pci) {

    u8		reg_id = 0x00;
    u8		value = 0x00;
    u8		counter = 0x00;

    for(counter = 0x00; counter < REGISTER_BUSY_COUNT; counter++){
        rt2x00_bbp_regread(rt2x00pci, 0x00, &value);
        if((value != 0xff) && (value != 0x00))
            goto continue_csr_init;
        NOTICE("Waiting for BBP register.\n");
    }

    ERROR("hardware problem, BBP register access failed, aborting.\n");
    return -EACCES;

  continue_csr_init:
    rt2x00_bbp_regwrite(rt2x00pci, 3, 0x02);
    rt2x00_bbp_regwrite(rt2x00pci, 4, 0x19);
    rt2x00_bbp_regwrite(rt2x00pci, 14, 0x1c);
    rt2x00_bbp_regwrite(rt2x00pci, 15, 0x30);
    rt2x00_bbp_regwrite(rt2x00pci, 16, 0xac);
    rt2x00_bbp_regwrite(rt2x00pci, 17, 0x48);
    rt2x00_bbp_regwrite(rt2x00pci, 18, 0x18);
    rt2x00_bbp_regwrite(rt2x00pci, 19, 0xff);
    rt2x00_bbp_regwrite(rt2x00pci, 20, 0x1e);
    rt2x00_bbp_regwrite(rt2x00pci, 21, 0x08);
    rt2x00_bbp_regwrite(rt2x00pci, 22, 0x08);
    rt2x00_bbp_regwrite(rt2x00pci, 23, 0x08);
    rt2x00_bbp_regwrite(rt2x00pci, 24, 0x70);
    rt2x00_bbp_regwrite(rt2x00pci, 25, 0x40);
    rt2x00_bbp_regwrite(rt2x00pci, 26, 0x08);
    rt2x00_bbp_regwrite(rt2x00pci, 27, 0x23);
    rt2x00_bbp_regwrite(rt2x00pci, 30, 0x10);
    rt2x00_bbp_regwrite(rt2x00pci, 31, 0x2b);
    rt2x00_bbp_regwrite(rt2x00pci, 32, 0xb9);
    rt2x00_bbp_regwrite(rt2x00pci, 34, 0x12);
    rt2x00_bbp_regwrite(rt2x00pci, 35, 0x50);
    rt2x00_bbp_regwrite(rt2x00pci, 39, 0xc4);
    rt2x00_bbp_regwrite(rt2x00pci, 40, 0x02);
    rt2x00_bbp_regwrite(rt2x00pci, 41, 0x60);
    rt2x00_bbp_regwrite(rt2x00pci, 53, 0x10);
    rt2x00_bbp_regwrite(rt2x00pci, 54, 0x18);
    rt2x00_bbp_regwrite(rt2x00pci, 56, 0x08);
    rt2x00_bbp_regwrite(rt2x00pci, 57, 0x10);
    rt2x00_bbp_regwrite(rt2x00pci, 58, 0x08);
    rt2x00_bbp_regwrite(rt2x00pci, 61, 0x6d);
    rt2x00_bbp_regwrite(rt2x00pci, 62, 0x10);

    DEBUG("Start reading EEPROM contents...\n");
    for(counter = 0; counter < EEPROM_BBP_SIZE; counter++){
        if(rt2x00pci->eeprom[counter] != 0xffff && rt2x00pci->eeprom[counter] != 0x0000){
            reg_id = rt2x00_get_field16(rt2x00pci->eeprom[counter], EEPROM_BBP_REG_ID);
            value = rt2x00_get_field16(rt2x00pci->eeprom[counter], EEPROM_BBP_VALUE);
            DEBUG("BBP reg_id: 0x%02x, value: 0x%02x.\n", reg_id, value);
            rt2x00_bbp_regwrite(rt2x00pci, reg_id, value);
        }
    }
    DEBUG("...End of EEPROM contents.\n");

    return 0;
}

/*
 * Device radio routines.
 * When the radio is switched on or off, the TX and RX
 * should always be reset using the TXCSR0 and RXCSR0 registers.
 * The radio itself is switched on and off using the PWRCSR0 register.
 */

static int rt2x00_dev_radio_on(struct _rt2x00_core * core) {

    struct _rt2x00_pci	*rt2x00pci = rt2x00_priv(core);
    u32			reg = 0x00000000;
    int retval;

    if(rt2x00_pci_alloc_rings(core))
        goto exit_fail;

    rt2x00_clear_ring(rt2x00pci, &rt2x00pci->rx);
    rt2x00_clear_ring(rt2x00pci, &rt2x00pci->tx);

    rt2x00_init_ring_register(rt2x00pci);

    if(rt2x00_init_registers(rt2x00pci))
        goto exit_fail;

    rt2x00_init_write_mac(rt2x00pci, core->rtnet_dev);

    if(rt2x00_init_bbp(rt2x00pci))
        goto exit_fail;

    /*
     * Clear interrupts.
     */
    rt2x00_register_read(rt2x00pci, CSR7, &reg);
    rt2x00_register_write(rt2x00pci, CSR7, reg);

    /* Register rtdm-irq */
    retval = rtdm_irq_request(&rt2x00pci->irq_handle,
                              core->rtnet_dev->irq, 
                              rt2x00_interrupt, 0, 
                              core->rtnet_dev->name, 
                              core->rtnet_dev);

    /*
     * Enable interrupts.
     */
    rt2x00_register_read(rt2x00pci, CSR8, &reg);
    rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, 0);
    rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
    rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
    rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
    rt2x00_set_field32(&reg, CSR8_RXDONE, 0);
    rt2x00_register_write(rt2x00pci, CSR8, reg);

    return 0;

  exit_fail:
    rt2x00_pci_free_rings(core);

    return -ENOMEM;
}

static int rt2x00_dev_radio_off(struct _rt2x00_core * core) {

    struct _rt2x00_pci	*rt2x00pci = rt2x00_priv(core);
    u32			reg = 0x00000000;
    int retval=0;

    rt2x00_register_write(rt2x00pci, PWRCSR0, cpu_to_le32(0x00000000));

    rt2x00_register_read(rt2x00pci, TXCSR0, &reg);
    rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
    rt2x00_register_write(rt2x00pci, TXCSR0, reg);

    rt2x00_register_read(rt2x00pci, RXCSR0, &reg);
    rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
    rt2x00_register_write(rt2x00pci, RXCSR0, reg);

    rt2x00_register_read(rt2x00pci, LEDCSR, &reg);
    rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
    rt2x00_register_write(rt2x00pci, LEDCSR, reg);

    rt2x00_register_read(rt2x00pci, CSR8, &reg);
    rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, 1);
    rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 1);
    rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 1);
    rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 1);
    rt2x00_set_field32(&reg, CSR8_RXDONE, 1);
    rt2x00_register_write(rt2x00pci, CSR8, reg);

    rt2x00_pci_free_rings(core);

    if((retval=rtdm_irq_free(&rt2x00pci->irq_handle)) != 0)
        ERROR("rtdm_irq_free=%d\n", retval);

    rt_stack_disconnect(core->rtnet_dev);

    return retval;
}


/*
 * Configuration handlers.
 */

static void
rt2x00_dev_update_autoresp(struct _rt2x00_pci *rt2x00pci, struct _rt2x00_config *config) {

    u32 reg = 0;

    DEBUG("Start.\n");

    rt2x00_register_read(rt2x00pci, TXCSR1, &reg);

    if(config->config_flags & CONFIG_AUTORESP)
        rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER , 1);
    else
        rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER , 0);

    rt2x00_register_write(rt2x00pci, TXCSR1, reg);
}

static void 
rt2x00_dev_update_bbpsens(struct _rt2x00_pci *rt2x00pci, struct _rt2x00_config *config) {

    rt2x00_bbp_regwrite(rt2x00pci, 0x11, config->bbpsens);
}

static void
rt2x00_dev_update_bssid(struct _rt2x00_pci *rt2x00pci, struct _rt2x00_config *config) {

    u32			reg[2];

    memset(&reg, 0x00, sizeof(reg));

    rt2x00_set_field32(&reg[0], CSR5_BYTE0, config->bssid[0]);
    rt2x00_set_field32(&reg[0], CSR5_BYTE1, config->bssid[1]);
    rt2x00_set_field32(&reg[0], CSR5_BYTE2, config->bssid[2]);
    rt2x00_set_field32(&reg[0], CSR5_BYTE3, config->bssid[3]);
    rt2x00_set_field32(&reg[1], CSR6_BYTE4, config->bssid[4]);
    rt2x00_set_field32(&reg[1], CSR6_BYTE5, config->bssid[5]);

    rt2x00_register_multiwrite(rt2x00pci, CSR5, &reg[0], sizeof(reg));
}

static void
rt2x00_dev_update_packet_filter(struct _rt2x00_pci *rt2x00pci, struct _rt2x00_config *config) {

    u32			reg = 0x00000000;

    DEBUG("Start.\n");

    rt2x00_register_read(rt2x00pci, RXCSR0, &reg);

    rt2x00_set_field32(&reg, RXCSR0_DROP_TODS, 0);
    rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME, 1);
    rt2x00_set_field32(&reg, RXCSR0_DROP_CRC, 1);
    rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, 1);
    rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL, 1);
    rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
    rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME, 1);

    /*
     * This looks like a bug, but for an unknown reason the register seems to swap the bits !!!
     */
    if(config->config_flags & CONFIG_DROP_BCAST)
        rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST, 1);
    else
        rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST, 0);
    
    if(config->config_flags & CONFIG_DROP_MCAST)
        rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 1);
    else
        rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);

    rt2x00_register_write(rt2x00pci, RXCSR0, reg);

}

static void
rt2x00_dev_update_channel(struct _rt2x00_pci *rt2x00pci, struct _rt2x00_config *config) {

    u8			txpower = rt2x00_get_txpower(&rt2x00pci->chip, config->txpower);
    u32			reg = 0x00000000;

    if(rt2x00_get_rf_value(&rt2x00pci->chip, config->channel, &rt2x00pci->channel)){
        ERROR("RF values for chip %04x and channel %d not found.\n", rt2x00_get_rf(&rt2x00pci->chip), config->channel);
        return;
    }

    /*
     * Set TXpower.
     */
    rt2x00_set_field32(&rt2x00pci->channel.rf3, RF3_TXPOWER, txpower);

    /*
     * For RT2525 we should first set the channel to half band higher.
     */
    if(rt2x00_rf(&rt2x00pci->chip, RF2525)){
        rt2x00_rf_regwrite(rt2x00pci, rt2x00pci->channel.rf1);
        rt2x00_rf_regwrite(rt2x00pci, rt2x00pci->channel.rf2 + cpu_to_le32(0x00000020));
        rt2x00_rf_regwrite(rt2x00pci, rt2x00pci->channel.rf3);
        if(rt2x00pci->channel.rf4)
            rt2x00_rf_regwrite(rt2x00pci, rt2x00pci->channel.rf4);
    }

    rt2x00_rf_regwrite(rt2x00pci, rt2x00pci->channel.rf1);
    rt2x00_rf_regwrite(rt2x00pci, rt2x00pci->channel.rf2);
    rt2x00_rf_regwrite(rt2x00pci, rt2x00pci->channel.rf3);
    if(rt2x00pci->channel.rf4)
        rt2x00_rf_regwrite(rt2x00pci, rt2x00pci->channel.rf4);

    /*
     * Channel 14 requires the Japan filter bit to be set.
     */
    rt2x00_bbp_regwrite(rt2x00pci, 70, (config->channel == 14) ? 0x4e : 0x46);

    msleep(1);

    /*
     * Clear false CRC during channel switch.
     */
    rt2x00_register_read(rt2x00pci, CNT0, &reg);

    DEBUG("Switching to channel %d. RF1: 0x%08x, RF2: 0x%08x, RF3: 0x%08x, RF4: 0x%08x.\n",
         config->channel, rt2x00pci->channel.rf1, rt2x00pci->channel.rf2,
         rt2x00pci->channel.rf3, rt2x00pci->channel.rf4);
}

static void
rt2x00_dev_update_rate(struct _rt2x00_pci *rt2x00pci, struct _rt2x00_config *config) {

    u32			value = 0x00000000;
    u32			reg = 0x00000000;
    u8			counter = 0x00;

    DEBUG("Start.\n");

    rt2x00_register_read(rt2x00pci, TXCSR1, &reg);

    value = config->sifs + (2 * config->slot_time) + config->plcp
        + get_preamble(config)
        + get_duration(ACK_SIZE, capabilities.bitrate[0]);
    rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, value);
    
    value = config->sifs + config->plcp
        + get_preamble(config)
        + get_duration(ACK_SIZE, capabilities.bitrate[0]);
    rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, value);

    rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, 0x18);
    rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);

    rt2x00_register_write(rt2x00pci, TXCSR1, reg);

    reg = 0x00000000;
    for(counter = 0; counter < 12; counter++){
        reg |= cpu_to_le32(0x00000001 << counter);
        if(capabilities.bitrate[counter] == config->bitrate)
            break;
    }

    rt2x00_register_write(rt2x00pci, ARCSR1, reg);
}

static void
rt2x00_dev_update_txpower(struct _rt2x00_pci *rt2x00pci, struct _rt2x00_config *config) {

    u8			txpower = rt2x00_get_txpower(&rt2x00pci->chip, config->txpower);
  
    DEBUG("Start.\n");

    rt2x00_set_field32(&rt2x00pci->channel.rf3, RF3_TXPOWER, txpower);
    rt2x00_rf_regwrite(rt2x00pci, rt2x00pci->channel.rf3);
}

static void
rt2x00_dev_update_antenna(struct _rt2x00_pci *rt2x00pci, struct _rt2x00_config *config) {

    u32			reg;