rt2500pci.h

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/*
 * EEPROM geography.
 */
#define EEPROM_GEOGRAPHY_GEO		FIELD16(8, 0x0f00)		/* Default geography setting for device. */

/*
 * EEPROM NIC config.
 */
#define EEPROM_NIC_CARDBUS_ACCEL	FIELD16(0, 0x0001)		/* 0: enable, 1: disable. */
#define EEPROM_NIC_DYN_BBP_TUNE		FIELD16(1, 0x0002)		/* 0: enable, 1: disable. */
#define EEPROM_NIC_CCK_TX_POWER		FIELD16(2, 0x000c)		/* CCK TX power compensation. */

/*
 * EEPROM TX power.
 */
#define EEPROM_TX_POWER1		FIELD16(0, 0x00ff)
#define EEPROM_TX_POWER2		FIELD16(8, 0xff00)

/*
 * EEPROM BBP.
 */
#define EEPROM_BBP_VALUE		FIELD16(0, 0x00ff)
#define EEPROM_BBP_REG_ID		FIELD16(8, 0xff00)

/*
 * EEPROM VERSION.
 */
#define EEPROM_VERSION_FAE		FIELD16(0, 0x00ff)		/* FAE release number. */
#define EEPROM_VERSION			FIELD16(8, 0xff00)

/*
 * DMA ring defines and data structures.
 */

/*
 * Size of a single descriptor.
 */
#define SIZE_DESCRIPTOR			48

/*
 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
 */
struct _txd{
    u32	word0;
#define TXD_W0_OWNER_NIC		FIELD32(0, 0x00000001)
#define TXD_W0_VALID			FIELD32(1, 0x00000002)
#define TXD_W0_RESULT			FIELD32(2, 0x0000001c)		/* Set by device. */
#define TXD_W0_RETRY_COUNT		FIELD32(5, 0x000000e0)		/* Set by device. */
#define TXD_W0_MORE_FRAG		FIELD32(8, 0x00000100)		/* Set by device. */
#define TXD_W0_ACK			FIELD32(9, 0x00000200)
#define TXD_W0_TIMESTAMP		FIELD32(10, 0x00000400)
#define TXD_W0_OFDM			FIELD32(11, 0x00000800)
#define TXD_W0_CIPHER_OWNER		FIELD32(12, 0x00001000)
#define TXD_W0_IFS			FIELD32(13, 0x00006000)
#define TXD_W0_RETRY_MODE		FIELD32(15, 0x00008000)
#define TXD_W0_DATABYTE_COUNT		FIELD32(16, 0x0fff0000)
#define TXD_W0_CIPHER_ALG		FIELD32(29, 0xe0000000)

    u32	word1;
#define TXD_W1_BUFFER_ADDRESS		FIELD32(0, 0xffffffff)

    u32	word2;
#define TXD_W2_IV_OFFSET		FIELD32(0, 0x0000003f)
#define TXD_W2_AIFS			FIELD32(6, 0x000000c0)
#define TXD_W2_CWMIN			FIELD32(8, 0x00000f00)
#define TXD_W2_CWMAX			FIELD32(12, 0x0000f000)

    u32	word3;
#define TXD_W3_PLCP_SIGNAL		FIELD32(0, 0x000000ff)
#define TXD_W3_PLCP_SERVICE		FIELD32(8, 0x0000ff00)
#define TXD_W3_PLCP_LENGTH_LOW		FIELD32(16, 0x00ff0000)
#define TXD_W3_PLCP_LENGTH_HIGH		FIELD32(24, 0xff000000)

    u32	word4;
#define TXD_W4_IV			FIELD32(0, 0xffffffff)

    u32	word5;
#define TXD_W5_EIV			FIELD32(0, 0xffffffff)

    u32	word6;
#define TXD_W6_KEY			FIELD32(0, 0xffffffff)

    u32	word7;
#define TXD_W7_KEY			FIELD32(0, 0xffffffff)

    u32	word8;
#define TXD_W8_KEY			FIELD32(0, 0xffffffff)

    u32	word9;
#define TXD_W9_KEY			FIELD32(0, 0xffffffff)

    u32	word10;
#define TXD_W10_RTS			FIELD32(0, 0x00000001)
#define TXD_W10_TX_RATE			FIELD32(0, 0x000000fe)		/* For module only. */
} __attribute__ ((packed));

/*
 * RX descriptor format for RX Ring.
 */
struct _rxd{
    u32 word0;
#define RXD_W0_OWNER_NIC		FIELD32(0, 0x00000001)
#define RXD_W0_UNICAST_TO_ME		FIELD32(1, 0x00000002)
#define RXD_W0_MULTICAST		FIELD32(2, 0x00000004)
#define RXD_W0_BROADCAST		FIELD32(3, 0x00000008)
#define RXD_W0_MY_BSS			FIELD32(4, 0x00000010)
#define RXD_W0_CRC			FIELD32(5, 0x00000020)
#define RXD_W0_OFDM			FIELD32(6, 0x00000040)
#define RXD_W0_PHYSICAL_ERROR		FIELD32(7, 0x00000080)
#define RXD_W0_CIPHER_OWNER		FIELD32(8, 0x00000100)
#define RXD_W0_ICV_ERROR		FIELD32(9, 0x00000200)
#define RXD_W0_IV_OFFSET		FIELD32(10, 0x0000fc00)
#define RXD_W0_DATABYTE_COUNT		FIELD32(16, 0x0fff0000)
#define RXD_W0_CIPHER_ALG		FIELD32(29, 0xe0000000)

    u32 word1;
#define RXD_W1_BUFFER_ADDRESS		FIELD32(0, 0xffffffff)

    u32 word2;
#define RXD_W2_BBR0			FIELD32(0, 0x000000ff)
#define RXD_W2_RSSI			FIELD32(8, 0x0000ff00)
#define RXD_W2_TA			FIELD32(16, 0xffff0000)

    u32 word3;
#define RXD_W3_TA			FIELD32(0, 0xffffffff)

    u32 word4;
#define RXD_W4_IV			FIELD32(0, 0xffffffff)

    u32 word5;
#define RXD_W5_EIV			FIELD32(0, 0xffffffff)

    u32 word6;
#define RXD_W6_KEY			FIELD32(0, 0xffffffff)

    u32 word7;
#define RXD_W7_KEY			FIELD32(0, 0xffffffff)

    u32 word8;
#define RXD_W8_KEY			FIELD32(0, 0xffffffff)

    u32 word9;
#define RXD_W9_KEY			FIELD32(0, 0xffffffff)

    u32 word10;
#define RXD_W10_DROP			FIELD32(0, 0x00000001)
} __attribute__ ((packed));


/*
 * _rt2x00_pci
 * This is the main structure which contains all variables required to communicate with the PCI device.
 */
struct _rt2x00_pci{

    /*
     * PCI device structure.
     */
    struct pci_dev			*pci_dev;

    /*
     * Chipset identification.
     */
    struct _rt2x00_chip		chip;

    /*
     * csr_addr
     * Base address of device registers, all exact register addresses are calculated from this address.
     */
    void __iomem			*csr_addr;

    /*
     * RF register values for current channel.
     */
    struct _rf_channel		channel;

    /*
     * EEPROM bus width.
     */
    u8				eeprom_width;

    u8				__pad;	/* For alignment only. */

    /*
     * EEPROM BBP data.
     */
    u16				eeprom[EEPROM_BBP_SIZE];

    /*
     * DMA packet ring.
     */
    struct _data_ring		rx;
    struct _data_ring		tx;

    rtdm_irq_t irq_handle;
    rtdm_lock_t lock;

} __attribute__ ((packed));

static int rt2x00_get_rf_value(const struct _rt2x00_chip *chip, const u8 channel, struct _rf_channel *rf_reg) {

    int			index = 0x00;

    index = rt2x00_get_channel_index(channel);
    if(index < 0)
        return -EINVAL;

    memset(rf_reg, 0x00, sizeof(*rf_reg));

    if(rt2x00_rf(chip, RF2522)){
        rf_reg->rf1 = 0x00002050;
        rf_reg->rf3 = 0x00000101;
        goto update_rf2_1;
    }
    if(rt2x00_rf(chip, RF2523)){
        rf_reg->rf1 = 0x00022010;
        rf_reg->rf3 = 0x000e0111;
        rf_reg->rf4 = 0x00000a1b;
        goto update_rf2_2;
    }
    if(rt2x00_rf(chip, RF2524)){
        rf_reg->rf1 = 0x00032020;
        rf_reg->rf3 = 0x00000101;
        rf_reg->rf4 = 0x00000a1b;
        goto update_rf2_2;
    }
    if(rt2x00_rf(chip, RF2525)){
        rf_reg->rf1 = 0x00022020;
        rf_reg->rf2 = 0x00080000;
        rf_reg->rf3 = 0x00060111;
        rf_reg->rf4 = 0x00000a1b;
        goto update_rf2_2;
    }
    if(rt2x00_rf(chip, RF2525E)){
        rf_reg->rf2 = 0x00080000;
        rf_reg->rf3 = 0x00060111;
        goto update_rf2_3;
    }
    if(rt2x00_rf(chip, RF5222)){
        rf_reg->rf3 = 0x00000101;
        goto update_rf2_3;
    }

    return -EINVAL;

  update_rf2_1: /* RF2522. */
    rf_reg->rf2 = 0x000c1fda + (index * 0x14);
    if(channel == 14)
        rf_reg->rf2 += 0x0000001c;
    goto exit;

  update_rf2_2: /* RF2523, RF2524, RF2525. */
    rf_reg->rf2 |= 0x00000c9e + (index * 0x04);
    if(rf_reg->rf2 & 0x00000040)
        rf_reg->rf2 += 0x00000040;
    if(channel == 14){
        rf_reg->rf2 += 0x08;
        rf_reg->rf4 &= ~0x00000018;
    }
    goto exit;

  update_rf2_3: /* RF2525E, RF5222. */
    if(OFDM_CHANNEL(channel)){
        rf_reg->rf1 = 0x00022020;
        rf_reg->rf2 |= 0x00001136 + (index * 0x04);
        if(rf_reg->rf2 & 0x00000040)
            rf_reg->rf2 += 0x00000040;
        if(channel == 14){
            rf_reg->rf2 += 0x04;
            rf_reg->rf4 = 0x00000a1b;
        }else{
            rf_reg->rf4 = 0x00000a0b;
        }
    }
    else if(UNII_LOW_CHANNEL(channel)){
        rf_reg->rf1 = 0x00022010;
        rf_reg->rf2 = 0x00018896 + (index * 0x04);
        rf_reg->rf4 = 0x00000a1f;
    }
    else if(HIPERLAN2_CHANNEL(channel)){
        rf_reg->rf1 = 0x00022010;
        rf_reg->rf2 = 0x00008802 + (index * 0x04);
        rf_reg->rf4 = 0x00000a0f;
    }
    else if(UNII_HIGH_CHANNEL(channel)){
        rf_reg->rf1 = 0x00022020;
        rf_reg->rf2 = 0x000090a6 + (index * 0x08);
        rf_reg->rf4 = 0x00000a07;
    }

  exit:
    rf_reg->rf1 = cpu_to_le32(rf_reg->rf1);
    rf_reg->rf2 = cpu_to_le32(rf_reg->rf2);
    rf_reg->rf3 = cpu_to_le32(rf_reg->rf3);
    rf_reg->rf4 = cpu_to_le32(rf_reg->rf4);

    return 0;	
}

/*
 * Get txpower value in dBm mathing the requested percentage.
 */
static inline u8
rt2x00_get_txpower(const struct _rt2x00_chip *chip, const u8 tx_power) {

    return tx_power / 100 * 31;

    /*
      if(tx_power <= 3)
      return 19;
      else if(tx_power <= 12)
      return 22;
      else if(tx_power <= 25)
      return 25;
      else if(tx_power <= 50)
      return 28;
      else if(tx_power <= 75)
      return 30;
      else if(tx_power <= 100)
      return 31;
    
      ERROR("Invalid tx_power.\n");
      return 31;
    */
}

/*
 * Ring handlers.
 */
static inline int rt2x00_pci_alloc_ring(
					struct _rt2x00_core *core,
					struct _data_ring *ring,
					const u8 ring_type,