rt2500pci.h

硬实时linux补丁rtai下的网络协议栈 最新

 * CSR15: Synchronization status register.
 */
#define CSR15_CFP			FIELD32(0, 0x00000001)		/* ASIC is in contention-free period. */
#define CSR15_ATIMW			FIELD32(1, 0x00000002)		/* ASIC is in ATIM window. */
#define CSR15_BEACON_SENT		FIELD32(2, 0x00000004)		/* Beacon is send. */

/*
 * CSR16: TSF timer register 0.
 */
#define CSR16_LOW_TSFTIMER		FIELD32(0, 0xffffffff)

/*
 * CSR17: TSF timer register 1.
 */
#define CSR17_HIGH_TSFTIMER		FIELD32(0, 0xffffffff)

/*
 * CSR18: IFS timer register 0.
 */
#define CSR18_SIFS			FIELD32(0, 0x000001ff)		/* sifs, default is 10 us. */
#define CSR18_PIFS			FIELD32(16, 0x01f00000)		/* pifs, default is 30 us. */

/*
 * CSR19: IFS timer register 1.
 */
#define CSR19_DIFS			FIELD32(0, 0x0000ffff)		/* difs, default is 50 us. */
#define CSR19_EIFS			FIELD32(16, 0xffff0000)		/* eifs, default is 364 us. */

/*
 * CSR20: Wakeup timer register.
 */
#define CSR20_DELAY_AFTER_TBCN		FIELD32(0, 0x0000ffff)		/* delay after tbcn expired in units of 1/16 TU. */
#define CSR20_TBCN_BEFORE_WAKEUP	FIELD32(16, 0x00ff0000)		/* number of beacon before wakeup. */
#define CSR20_AUTOWAKE			FIELD32(24, 0x01000000)		/* enable auto wakeup / sleep mechanism. */

/*
 * CSR21: EEPROM control register.
 */
#define CSR21_RELOAD			FIELD32(0, 0x00000001)		/* Write 1 to reload eeprom content. */
#define CSR21_EEPROM_DATA_CLOCK		FIELD32(1, 0x00000002)
#define CSR21_EEPROM_CHIP_SELECT	FIELD32(2, 0x00000004)
#define CSR21_EEPROM_DATA_IN		FIELD32(3, 0x00000008)
#define CSR21_EEPROM_DATA_OUT		FIELD32(4, 0x00000010)
#define CSR21_TYPE_93C46		FIELD32(5, 0x00000020)		/* 1: 93c46, 0:93c66. */

/*
 * CSR22: CFP control register.
 */
#define CSR22_CFP_DURATION_REMAIN	FIELD32(0, 0x0000ffff)		/* cfp duration remain, in units of TU. */
#define CSR22_RELOAD_CFP_DURATION	FIELD32(16, 0x00010000)		/* Write 1 to reload cfp duration remain. */

/*
 * TX / RX Registers.
 * Some values are set in TU, whereas 1 TU == 1024 us.
 */

/*
 * TXCSR0: TX Control Register.
 */
#define TXCSR0_KICK_TX			FIELD32(0, 0x00000001)		/* kick tx ring. */
#define TXCSR0_KICK_ATIM		FIELD32(1, 0x00000002)		/* kick atim ring. */
#define TXCSR0_KICK_PRIO		FIELD32(2, 0x00000004)		/* kick priority ring. */
#define TXCSR0_ABORT			FIELD32(3, 0x00000008)		/* abort all transmit related ring operation. */

/*
 * TXCSR1: TX Configuration Register.
 */
#define TXCSR1_ACK_TIMEOUT		FIELD32(0, 0x000001ff)		/* ack timeout, default = sifs + 2*slottime + acktime @ 1mbps. */
#define TXCSR1_ACK_CONSUME_TIME		FIELD32(9, 0x0003fe00)		/* ack consume time, default = sifs + acktime @ 1mbps. */
#define TXCSR1_TSF_OFFSET		FIELD32(18, 0x00fc0000)		/* insert tsf offset. */
#define TXCSR1_AUTORESPONDER		FIELD32(24, 0x01000000)		/* enable auto responder which include ack & cts. */

/*
 * TXCSR2: Tx descriptor configuration register.
 */
#define TXCSR2_TXD_SIZE			FIELD32(0, 0x000000ff)		/* tx descriptor size, default is 48. */
#define TXCSR2_NUM_TXD			FIELD32(8, 0x0000ff00)		/* number of txd in ring. */
#define TXCSR2_NUM_ATIM			FIELD32(16, 0x00ff0000)		/* number of atim in ring. */
#define TXCSR2_NUM_PRIO			FIELD32(24, 0xff000000)		/* number of priority in ring. */

/*
 * TXCSR3: TX Ring Base address register.
 */
#define TXCSR3_TX_RING_REGISTER		FIELD32(0, 0xffffffff)

/*
 * TXCSR4: TX Atim Ring Base address register.
 */
#define TXCSR4_ATIM_RING_REGISTER	FIELD32(0, 0xffffffff)

/*
 * TXCSR5: TX Prio Ring Base address register.
 */
#define TXCSR5_PRIO_RING_REGISTER	FIELD32(0, 0xffffffff)

/*
 * TXCSR6: Beacon Base address register.
 */
#define TXCSR6_BEACON_REGISTER		FIELD32(0, 0xffffffff)

/*
 * TXCSR7: Auto responder control register.
 */
#define TXCSR7_AR_POWERMANAGEMENT	FIELD32(0, 0x00000001)		/* auto responder power management bit. */

/*
 * TXCSR8: CCK Tx BBP register.
 */
#define TXCSR8_CCK_SIGNAL		FIELD32(0, 0x000000ff)		/* BBP rate field address for CCK. */
#define TXCSR8_CCK_SERVICE		FIELD32(8, 0x0000ff00)		/* BBP service field address for CCK. */
#define TXCSR8_CCK_LENGTH_LOW		FIELD32(16, 0x00ff0000)		/* BBP length low byte address for CCK. */
#define TXCSR8_CCK_LENGTH_HIGH		FIELD32(24, 0xff000000)		/* BBP length high byte address for CCK. */

/* 
 * TXCSR9: OFDM TX BBP registers
 */
#define TXCSR9_OFDM_RATE		FIELD32(0, 0x000000ff)		/* BBP rate field address for OFDM. */
#define TXCSR9_OFDM_SERVICE		FIELD32(8, 0x0000ff00)		/* BBP service field address for OFDM. */
#define TXCSR9_OFDM_LENGTH_LOW		FIELD32(16, 0x00ff0000)		/* BBP length low byte address for OFDM. */
#define TXCSR9_OFDM_LENGTH_HIGH		FIELD32(24, 0xff000000)		/* BBP length high byte address for OFDM. */

/*
 * RXCSR0: RX Control Register.
 */
#define RXCSR0_DISABLE_RX		FIELD32(0, 0x00000001)		/* disable rx engine. */
#define RXCSR0_DROP_CRC			FIELD32(1, 0x00000002)		/* drop crc error. */
#define RXCSR0_DROP_PHYSICAL		FIELD32(2, 0x00000004)		/* drop physical error. */
#define RXCSR0_DROP_CONTROL		FIELD32(3, 0x00000008)		/* drop control frame. */
#define RXCSR0_DROP_NOT_TO_ME		FIELD32(4, 0x00000010)		/* drop not to me unicast frame. */
#define RXCSR0_DROP_TODS		FIELD32(5, 0x00000020)		/* drop frame tods bit is true. */
#define RXCSR0_DROP_VERSION_ERROR	FIELD32(6, 0x00000040)		/* drop version error frame. */
#define RXCSR0_PASS_CRC			FIELD32(7, 0x00000080)		/* pass all packets with crc attached. */
#define RXCSR0_PASS_PLCP		FIELD32(8, 0x00000100)		/* Pass all packets with 4 bytes PLCP attached. */
#define RXCSR0_DROP_MCAST		FIELD32(9, 0x00000200)		/* Drop multicast frames. */
#define RXCSR0_DROP_BCAST		FIELD32(10, 0x00000400)		/* Drop broadcast frames. */
#define RXCSR0_ENABLE_QOS		FIELD32(11, 0x00000800)		/* Accept QOS data frame and parse QOS field. */

/*
 * RXCSR1: RX descriptor configuration register.
 */
#define RXCSR1_RXD_SIZE			FIELD32(0, 0x000000ff)		/* rx descriptor size, default is 32b. */
#define RXCSR1_NUM_RXD			FIELD32(8, 0x0000ff00)		/* number of rxd in ring. */

/*
 * RXCSR2: RX Ring base address register.
 */
#define RXCSR2_RX_RING_REGISTER		FIELD32(0, 0xffffffff)

/*
 * RXCSR3: BBP ID register for Rx operation.
 */
#define RXCSR3_BBP_ID0			FIELD32(0, 0x0000007f)		/* bbp register 0 id. */
#define RXCSR3_BBP_ID0_VALID		FIELD32(7, 0x00000080)		/* bbp register 0 id is valid or not. */
#define RXCSR3_BBP_ID1			FIELD32(8, 0x00007f00)		/* bbp register 1 id. */
#define RXCSR3_BBP_ID1_VALID		FIELD32(15, 0x00008000)		/* bbp register 1 id is valid or not. */
#define RXCSR3_BBP_ID2			FIELD32(16, 0x007f0000)		/* bbp register 2 id. */
#define RXCSR3_BBP_ID2_VALID		FIELD32(23, 0x00800000)		/* bbp register 2 id is valid or not. */
#define RXCSR3_BBP_ID3			FIELD32(24, 0x7f000000)		/* bbp register 3 id. */
#define RXCSR3_BBP_ID3_VALID		FIELD32(31, 0x80000000)		/* bbp register 3 id is valid or not. */

/*
 * ARCSR1: Auto Responder PLCP config register 1.
 */
#define ARCSR1_AR_BBP_DATA2		FIELD32(0, 0x000000ff)		/* Auto responder BBP register 2 data. */
#define ARCSR1_AR_BBP_ID2		FIELD32(8, 0x0000ff00)		/* Auto responder BBP register 2 Id. */
#define ARCSR1_AR_BBP_DATA3		FIELD32(16, 0x00ff0000)		/* Auto responder BBP register 3 data. */
#define ARCSR1_AR_BBP_ID3		FIELD32(24, 0xff000000)		/* Auto responder BBP register 3 Id. */

/*
 * Miscellaneous Registers.
 * Some values are set in TU, whereas 1 TU == 1024 us.
 */

/*
 * PCISR: PCI control register.
 */
#define PCICSR_BIG_ENDIAN		FIELD32(0, 0x00000001)		/* 1: big endian, 0: little endian. */
#define PCICSR_RX_TRESHOLD		FIELD32(1, 0x00000006)		/* rx threshold in dw to start pci access */
									/* 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw. */
#define PCICSR_TX_TRESHOLD		FIELD32(3, 0x00000018)		/* tx threshold in dw to start pci access */
									/* 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward. */
#define PCICSR_BURST_LENTH		FIELD32(5, 0x00000060)		/* pci burst length */
									/* 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw. */
#define PCICSR_ENABLE_CLK		FIELD32(7, 0x00000080)		/* enable clk_run, */
									/* pci clock can't going down to non-operational. */
#define PCICSR_READ_MULTIPLE		FIELD32(8, 0x00000100)		/* Enable memory read multiple. */
#define PCICSR_WRITE_INVALID		FIELD32(9, 0x00000200)		/* Enable memory write & invalid. */

/*
 * PWRCSR1: Manual power control / status register.
 * state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
 */
#define PWRCSR1_SET_STATE		FIELD32(0, 0x00000001)		/* set state. Write 1 to trigger, self cleared. */
#define PWRCSR1_BBP_DESIRE_STATE	FIELD32(1, 0x00000006)		/* BBP desired state. */
#define PWRCSR1_RF_DESIRE_STATE		FIELD32(3, 0x00000018)		/* RF desired state. */
#define PWRCSR1_BBP_CURR_STATE		FIELD32(5, 0x00000060)		/* BBP current state. */
#define PWRCSR1_RF_CURR_STATE		FIELD32(7, 0x00000180)		/* RF current state. */
#define PWRCSR1_PUT_TO_SLEEP		FIELD32(9, 0x00000200)		/* put to sleep. Write 1 to trigger, self cleared. */

/*
 * TIMECSR: Timer control register.
 */
#define TIMECSR_US_COUNT		FIELD32(0, 0x000000ff)		/* 1 us timer count in units of clock cycles. */
#define TIMECSR_US_64_COUNT		FIELD32(8, 0x0000ff00)		/* 64 us timer count in units of 1 us timer. */
#define TIMECSR_BEACON_EXPECT		FIELD32(16, 0x00070000)		/* Beacon expect window. */

/*
 * MACCSR1: MAC configuration register 1.
 */
#define MACCSR1_KICK_RX			FIELD32(0, 0x00000001)		/* kick one-shot rx in one-shot rx mode. */
#define MACCSR1_ONESHOT_RXMODE		FIELD32(1, 0x00000002)		/* enable one-shot rx mode for debugging. */
#define MACCSR1_BBPRX_RESET_MODE	FIELD32(2, 0x00000004)		/* ralink bbp rx reset mode. */
#define MACCSR1_AUTO_TXBBP		FIELD32(3, 0x00000008)		/* auto tx logic access bbp control register. */
#define MACCSR1_AUTO_RXBBP		FIELD32(4, 0x00000010)		/* auto rx logic access bbp control register. */
#define MACCSR1_LOOPBACK		FIELD32(5, 0x00000060)		/* loopback mode. */
									/* 0: normal, 1: internal, 2: external, 3:rsvd. */
#define MACCSR1_INTERSIL_IF		FIELD32(7, 0x00000080)		/* intersil if calibration pin. */

/*
 * RALINKCSR: Ralink Rx auto-reset BBCR.
 */
#define RALINKCSR_AR_BBP_DATA0		FIELD32(0, 0x000000ff)		/* auto reset bbp register 0 data. */
#define RALINKCSR_AR_BBP_ID0		FIELD32(8, 0x00007f00)		/* auto reset bbp register 0 id. */
#define RALINKCSR_AR_BBP_VALID0		FIELD32(15, 0x00008000)		/* auto reset bbp register 0 valid. */
#define RALINKCSR_AR_BBP_DATA1		FIELD32(16, 0x00ff0000)		/* auto reset bbp register 1 data. */
#define RALINKCSR_AR_BBP_ID1		FIELD32(24, 0x7f000000)		/* auto reset bbp register 1 id. */
#define RALINKCSR_AR_BBP_VALID1		FIELD32(31, 0x80000000)		/* auto reset bbp register 1 valid. */

/*
 * BCNCSR: Beacon interval control register.
 */
#define BCNCSR_CHANGE			FIELD32(0, 0x00000001)		/* write one to change beacon interval. */
#define BCNCSR_DELTATIME		FIELD32(1, 0x0000001e)		/* the delta time value. */
#define BCNCSR_NUM_BEACON		FIELD32(5, 0x00001fe0)		/* number of beacon according to mode. */
#define BCNCSR_MODE			FIELD32(13, 0x00006000)		/* please refer to asic specs. */
#define BCNCSR_PLUS			FIELD32(15, 0x00008000)		/* plus or minus delta time value. */

/*
 * BBPCSR: BBP serial control register.
 */
#define BBPCSR_VALUE			FIELD32(0, 0x000000ff)		/* register value to program into bbp. */
#define BBPCSR_REGNUM			FIELD32(8, 0x00007f00)		/* selected bbp register. */
#define BBPCSR_BUSY			FIELD32(15, 0x00008000)		/* 1: asic is busy execute bbp programming. */
#define BBPCSR_WRITE_CONTROL		FIELD32(16, 0x00010000)		/* 1: write bbp, 0: read bbp. */

/*
 * RFCSR: RF serial control register.
 */
#define RFCSR_VALUE			FIELD32(0, 0x00ffffff)		/* register value + id to program into rf/if. */
#define RFCSR_NUMBER_OF_BITS		FIELD32(24, 0x1f000000)		/* number of bits used in value (i:20, rfmd:22). */
#define RFCSR_IF_SELECT			FIELD32(29, 0x20000000)		/* chip to program: 0: rf, 1: if. */
#define RFCSR_PLL_LD			FIELD32(30, 0x40000000)		/* rf pll_ld status. */
#define RFCSR_BUSY			FIELD32(31, 0x80000000)		/* 1: asic is busy execute rf programming. */

/*
 * LEDCSR: LED control register.
 */
#define LEDCSR_ON_PERIOD		FIELD32(0, 0x000000ff)		/* on period, default 70ms. */
#define LEDCSR_OFF_PERIOD		FIELD32(8, 0x0000ff00)		/* off period, default 30ms. */
#define LEDCSR_LINK			FIELD32(16, 0x00010000)		/* 0: linkoff, 1: linkup. */
#define LEDCSR_ACTIVITY			FIELD32(17, 0x00020000)		/* 0: idle, 1: active. */
#define LEDCSR_LINK_POLARITY		FIELD32(18, 0x00040000)		/* 0: active low, 1: active high. */
#define LEDCSR_ACTIVITY_POLARITY	FIELD32(19, 0x00080000)		/* 0: active low, 1: active high. */
#define LEDCSR_LED_DEFAULT		FIELD32(20, 0x00100000)		/* LED state for "enable" 0: ON, 1: OFF. */

/*
 * GPIOCSR: GPIO control register.
 */
#define GPIOCSR_BIT0			FIELD32(0, 0x00000001)
#define GPIOCSR_BIT1			FIELD32(1, 0x00000002)
#define GPIOCSR_BIT2			FIELD32(2, 0x00000004)
#define GPIOCSR_BIT3			FIELD32(3, 0x00000008)
#define GPIOCSR_BIT4			FIELD32(4, 0x00000010)
#define GPIOCSR_BIT5			FIELD32(5, 0x00000020)
#define GPIOCSR_BIT6			FIELD32(6, 0x00000040)
#define GPIOCSR_BIT7			FIELD32(7, 0x00000080)
#define GPIOCSR_DIR0			FIELD32(8, 0x00000100)
#define GPIOCSR_DIR1			FIELD32(9, 0x00000200)
#define GPIOCSR_DIR2			FIELD32(10, 0x00000400)
#define GPIOCSR_DIR3			FIELD32(11, 0x00000800)
#define GPIOCSR_DIR4			FIELD32(12, 0x00001000)
#define GPIOCSR_DIR5			FIELD32(13, 0x00002000)
#define GPIOCSR_DIR6			FIELD32(14, 0x00004000)
#define GPIOCSR_DIR7			FIELD32(15, 0x00008000)

/*
 * BCNCSR1: Tx BEACON offset time control register.
 */
#define BCNCSR1_PRELOAD			FIELD32(0, 0x0000ffff)		/* beacon timer offset in units of usec. */
#define BCNCSR1_BEACON_CWMIN		FIELD32(16, 0x000f0000)		/* 2^CwMin. */

/*
 * MACCSR2: TX_PE to RX_PE turn-around time control register
 */
#define MACCSR2_DELAY			FIELD32(0, 0x000000ff)		/* RX_PE low width, in units of pci clock cycle. */

/*
 * SECCSR1_RT2509: WEP control register 
 */
#define SECCSR1_KICK_ENCRYPT		FIELD32(0, 0x00000001)		/* Kick encryption engine, self-clear. */
#define SECCSR1_ONE_SHOT		FIELD32(1, 0x00000002)		/* 0: ring mode, 1: One shot only mode. */
#define SECCSR1_DESC_ADDRESS		FIELD32(2, 0xfffffffc)		/* Descriptor physical address of frame. */

/*
 * RF registers
 */
#define RF1_TUNER			FIELD32(17, 0x00020000)
#define RF3_TUNER			FIELD32(8, 0x00000100)
#define RF3_TXPOWER			FIELD32(9, 0x00003e00)

/*
 * EEPROM content format.
 * The wordsize of the EEPROM is 16 bits.
 */

/*
 * EEPROM operation defines.
 */
#define EEPROM_WIDTH_93c46		6
#define EEPROM_WIDTH_93c66		8
#define EEPROM_WRITE_OPCODE		0x05
#define EEPROM_READ_OPCODE		0x06

/*
 * EEPROM antenna.
 */
#define EEPROM_ANTENNA_NUM		FIELD16(0, 0x0003)		/* Number of antenna's. */
#define EEPROM_ANTENNA_TX_DEFAULT	FIELD16(2, 0x000c)		/* Default antenna 0: diversity, 1: A, 2: B. */
#define EEPROM_ANTENNA_RX_DEFAULT	FIELD16(4, 0x0030)		/* Default antenna 0: diversity, 1: A, 2: B. */
#define EEPROM_ANTENNA_LED_MODE		FIELD16(6, 0x01c0)		/* 0: default, 1: TX/RX activity, */
									/* 2: Single LED (ignore link), 3: reserved. */
#define EEPROM_ANTENNA_DYN_TXAGC	FIELD16(9, 0x0200)		/* Dynamic TX AGC control. */
#define EEPROM_ANTENNA_HARDWARE_RADIO	FIELD16(10, 0x0400)		/* 1: Hardware controlled radio. Read GPIO0. */
#define EEPROM_ANTENNA_RF_TYPE		FIELD16(11, 0xf800)		/* rf_type of this adapter. */