rt2500pci.h

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/* rt2500pci.h
 *
 * Copyright (C) 2004 - 2005 rt2x00-2.0.0-b3 SourceForge Project
 *	                     <http://rt2x00.serialmonkey.com>
 *               2006        rtnet adaption by Daniel Gregorek 
 *                           <[e-mail]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the
 * Free Software Foundation, Inc.,
 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

/*
 *	Module: rt2500pci
 * Abstract: Data structures and registers for the rt2500pci module.
 * Supported chipsets: RT2560.
 */

#ifndef RT2500PCI_H
#define RT2500PCI_H

/*
 * RT chip defines
 */
#define RT2560				0x0201

/*
 * RF chip defines
 */
#define RF2522				0x0200
#define RF2523				0x0201
#define RF2524				0x0202
#define RF2525				0x0203
#define RF2525E				0x0204
#define RF5222				0x0210

/*
 * Control/Status Registers(CSR).
 */
#define CSR0				0x0000		/* ASIC revision number. */
#define CSR1				0x0004		/* System control register. */
#define CSR2				0x0008		/* System admin status register (invalid). */
#define CSR3				0x000c		/* STA MAC address register 0. */
#define CSR4				0x0010		/* STA MAC address register 1. */
#define CSR5				0x0014		/* BSSID register 0. */
#define CSR6				0x0018		/* BSSID register 1. */
#define CSR7				0x001c		/* Interrupt source register. */
#define CSR8				0x0020		/* Interrupt mask register. */
#define CSR9				0x0024		/* Maximum frame length register. */
#define SECCSR0				0x0028		/* WEP control register. */
#define CSR11				0x002c		/* Back-off control register. */
#define CSR12				0x0030		/* Synchronization configuration register 0. */
#define CSR13				0x0034		/* Synchronization configuration register 1. */
#define CSR14				0x0038		/* Synchronization control register. */
#define CSR15				0x003c		/* Synchronization status register. */
#define CSR16				0x0040		/* TSF timer register 0. */
#define CSR17				0x0044		/* TSF timer register 1. */
#define CSR18				0x0048		/* IFS timer register 0. */
#define CSR19				0x004c		/* IFS timer register 1. */
#define CSR20				0x0050		/* WakeUp register. */
#define CSR21				0x0054		/* EEPROM control register. */
#define CSR22				0x0058		/* CFP Control Register. */

/*
 * Transmit related CSRs.
 */
#define TXCSR0				0x0060		/* TX control register. */
#define TXCSR1				0x0064		/* TX configuration register. */
#define TXCSR2				0x0068		/* TX descriptor configuratioon register. */
#define TXCSR3				0x006c		/* TX Ring Base address register. */
#define TXCSR4				0x0070		/* TX Atim Ring Base address register. */
#define TXCSR5				0x0074		/* TX Prio Ring Base address register. */
#define TXCSR6				0x0078		/* Beacon base address. */
#define TXCSR7				0x007c		/* AutoResponder Control Register. */
#define TXCSR8				0x0098		/* CCK TX BBP registers. */
#define TXCSR9				0x0094		/* OFDM TX BBP registers. */

/*
 * Receive related CSRs.
 */
#define RXCSR0				0x0080		/* RX control register. */
#define RXCSR1				0x0084		/* RX descriptor configuration register. */
#define RXCSR2				0x0088		/* RX Ring base address register. */
#define RXCSR3				0x0090		/* BBP ID register 0 */
#define ARCSR1				0x009c		/* Auto Responder PLCP config register 1. */

/*
 * PCI control CSRs.
 */
#define PCICSR				0x008c		/* PCI control register. */

/*
 * Statistic Register.
 */
#define CNT0				0x00a0		/* FCS error count. */
#define TIMECSR2			0x00a8
#define CNT1				0x00ac		/* PLCP error count. */
#define CNT2				0x00b0		/* long error count. */
#define TIMECSR3			0x00b4
#define CNT3				0x00b8		/* CCA false alarm count. */
#define CNT4				0x00bc		/* Rx FIFO overflow count. */
#define CNT5				0x00c0		/* Tx FIFO underrun count. */

/*
 * Baseband Control Register.
 */
#define PWRCSR0				0x00c4		/* Power mode configuration. */
#define PSCSR0				0x00c8		/* Power state transition time. */
#define PSCSR1				0x00cc		/* Power state transition time. */
#define PSCSR2				0x00d0		/* Power state transition time. */
#define PSCSR3				0x00d4		/* Power state transition time. */
#define PWRCSR1				0x00d8		/* Manual power control / status. */
#define TIMECSR				0x00dc		/* Timer control. */
#define MACCSR0				0x00e0		/* MAC configuration. */
#define MACCSR1				0x00e4		/* MAC configuration. */
#define RALINKCSR			0x00e8		/* Ralink Auto-reset register. */
#define BCNCSR				0x00ec		/* Beacon interval control register. */

/*
 * BBP / RF / IF Control Register.
 */
#define BBPCSR				0x00f0		/* BBP serial control. */
#define RFCSR				0x00f4		/* RF serial control. */
#define LEDCSR				0x00f8		/* LED control register */

#define SECCSR3				0x00fc		/* AES control register. */

/*
 * ASIC pointer information.
 */
#define RXPTR				0x0100		/* Current RX ring address. */
#define TXPTR				0x0104		/* Current Tx ring address. */
#define PRIPTR				0x0108		/* Current Priority ring address. */
#define ATIMPTR				0x010c		/* Current ATIM ring address. */

#define TXACKCSR0			0x0110		/* TX ACK timeout. */
#define ACKCNT0				0x0114		/* TX ACK timeout count. */
#define ACKCNT1				0x0118		/* RX ACK timeout count. */

/*
 * GPIO and others.
 */
#define GPIOCSR				0x0120		/* GPIO. */
#define FIFOCSR0			0x0128		/* TX FIFO pointer. */
#define FIFOCSR1			0x012c		/* RX FIFO pointer. */
#define BCNCSR1				0x0130		/* Tx BEACON offset time, unit: 1 usec. */
#define MACCSR2				0x0134		/* TX_PE to RX_PE delay time, unit: 1 PCI clock cycle. */
#define TESTCSR				0x0138		/* TEST mode selection register. */
#define ARCSR2				0x013c		/* 1 Mbps ACK/CTS PLCP. */
#define ARCSR3				0x0140		/* 2 Mbps ACK/CTS PLCP. */
#define ARCSR4				0x0144		/* 5.5 Mbps ACK/CTS PLCP. */
#define ARCSR5				0x0148		/* 11 Mbps ACK/CTS PLCP. */
#define ARTCSR0				0x014c		/* ACK/CTS payload consumed time for 1/2/5.5/11 mbps. */
#define ARTCSR1				0x0150		/* OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps. */
#define ARTCSR2				0x0154		/* OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps. */
#define SECCSR1				0x0158		/* WEP control register. */
#define BBPCSR1				0x015c		/* BBP TX configuration. */
#define DBANDCSR0			0x0160		/* Dual band configuration register 0. */
#define DBANDCSR1			0x0164		/* Dual band configuration register 1. */
#define BBPPCSR				0x0168		/* BBP Pin control register. */
#define DBGSEL0				0x016c		/* MAC special debug mode selection register 0. */
#define DBGSEL1				0x0170		/* MAC special debug mode selection register 1. */
#define BISTCSR				0x0174		/* BBP BIST register. */
#define MCAST0				0x0178		/* multicast filter register 0. */
#define MCAST1				0x017c		/* multicast filter register 1. */
#define UARTCSR0			0x0180		/* UART1 TX register. */
#define UARTCSR1			0x0184		/* UART1 RX register. */
#define UARTCSR3			0x0188		/* UART1 frame control register. */
#define UARTCSR4			0x018c		/* UART1 buffer control register. */
#define UART2CSR0			0x0190		/* UART2 TX register. */
#define UART2CSR1			0x0194		/* UART2 RX register. */
#define UART2CSR3			0x0198		/* UART2 frame control register. */
#define UART2CSR4			0x019c		/* UART2 buffer control register. */

/*
 * EEPROM addresses
 */
#define EEPROM_ANTENNA			0x10
#define EEPROM_GEOGRAPHY		0x12
#define EEPROM_BBP_START		0x13
#define EEPROM_BBP_END			0x22

#define EEPROM_BBP_SIZE			16

/*
 * CSR Registers.
 * Some values are set in TU, whereas 1 TU == 1024 us.
 */

/*
 * CSR1: System control register.
 */
#define CSR1_SOFT_RESET			FIELD32(0, 0x00000001)		/* Software reset, 1: reset, 0: normal. */
#define CSR1_BBP_RESET			FIELD32(1, 0x00000002)		/* Hardware reset, 1: reset, 0, release. */
#define CSR1_HOST_READY			FIELD32(2, 0x00000004)		/* Host ready after initialization. */

/*
 * CSR3: STA MAC address register 0.
 */
#define CSR3_BYTE0			FIELD32(0, 0x000000ff)		/* MAC address byte 0. */
#define CSR3_BYTE1			FIELD32(8, 0x0000ff00)		/* MAC address byte 1. */
#define CSR3_BYTE2			FIELD32(16, 0x00ff0000)		/* MAC address byte 2. */
#define CSR3_BYTE3			FIELD32(24, 0xff000000)		/* MAC address byte 3. */

/*
 * CSR4: STA MAC address register 1.
 */
#define CSR4_BYTE4			FIELD32(0, 0x000000ff)		/* MAC address byte 4. */
#define CSR4_BYTE5			FIELD32(8, 0x0000ff00)		/* MAC address byte 5. */

/*
 * CSR5: BSSID register 0.
 */
#define CSR5_BYTE0			FIELD32(0, 0x000000ff)		/* BSSID address byte 0. */
#define CSR5_BYTE1			FIELD32(8, 0x0000ff00)		/* BSSID address byte 1. */
#define CSR5_BYTE2			FIELD32(16, 0x00ff0000)		/* BSSID address byte 2. */
#define CSR5_BYTE3			FIELD32(24, 0xff000000)		/* BSSID address byte 3. */

/*
 * CSR6: BSSID register 1.
 */
#define CSR6_BYTE4			FIELD32(0, 0x000000ff)		/* BSSID address byte 4. */
#define CSR6_BYTE5			FIELD32(8, 0x0000ff00)		/* BSSID address byte 5. */

/*
 * CSR7: Interrupt source register.
 * Write 1 to clear.
 */
#define CSR7_TBCN_EXPIRE		FIELD32(0, 0x00000001)		/* beacon timer expired interrupt. */
#define CSR7_TWAKE_EXPIRE		FIELD32(1, 0x00000002)		/* wakeup timer expired interrupt. */
#define CSR7_TATIMW_EXPIRE		FIELD32(2, 0x00000004)		/* timer of atim window expired interrupt. */
#define CSR7_TXDONE_TXRING		FIELD32(3, 0x00000008)		/* tx ring transmit done interrupt. */
#define CSR7_TXDONE_ATIMRING		FIELD32(4, 0x00000010)		/* atim ring transmit done interrupt. */
#define CSR7_TXDONE_PRIORING		FIELD32(5, 0x00000020)		/* priority ring transmit done interrupt. */
#define CSR7_RXDONE			FIELD32(6, 0x00000040)		/* receive done interrupt. */
#define CSR7_DECRYPTION_DONE		FIELD32(7, 0x00000080)		/* Decryption done interrupt. */
#define CSR7_ENCRYPTION_DONE		FIELD32(8, 0x00000100)		/* Encryption done interrupt. */
#define CSR7_UART1_TX_TRESHOLD		FIELD32(9, 0x00000200)		/* UART1 TX reaches threshold. */
#define CSR7_UART1_RX_TRESHOLD		FIELD32(10, 0x00000400)		/* UART1 RX reaches threshold. */
#define CSR7_UART1_IDLE_TRESHOLD	FIELD32(11, 0x00000800)		/* UART1 IDLE over threshold. */
#define CSR7_UART1_TX_BUFF_ERROR	FIELD32(12, 0x00001000)		/* UART1 TX buffer error. */
#define CSR7_UART1_RX_BUFF_ERROR	FIELD32(13, 0x00002000)		/* UART1 RX buffer error. */
#define CSR7_UART2_TX_TRESHOLD		FIELD32(14, 0x00004000)		/* UART2 TX reaches threshold. */
#define CSR7_UART2_RX_TRESHOLD		FIELD32(15, 0x00008000)		/* UART2 RX reaches threshold. */
#define CSR7_UART2_IDLE_TRESHOLD	FIELD32(16, 0x00010000)		/* UART2 IDLE over threshold. */
#define CSR7_UART2_TX_BUFF_ERROR	FIELD32(17, 0x00020000)		/* UART2 TX buffer error. */
#define CSR7_UART2_RX_BUFF_ERROR	FIELD32(18, 0x00040000)		/* UART2 RX buffer error. */
#define CSR7_TIMER_CSR3_EXPIRE		FIELD32(19, 0x00080000)		/* TIMECSR3 timer expired (802.1H quiet period). */

/*
 * CSR8: Interrupt mask register.
 * Write 1 to mask interrupt.
 */
#define CSR8_TBCN_EXPIRE		FIELD32(0, 0x00000001)		/* beacon timer expired interrupt. */
#define CSR8_TWAKE_EXPIRE		FIELD32(1, 0x00000002)		/* wakeup timer expired interrupt. */
#define CSR8_TATIMW_EXPIRE		FIELD32(2, 0x00000004)		/* timer of atim window expired interrupt. */
#define CSR8_TXDONE_TXRING		FIELD32(3, 0x00000008)		/* tx ring transmit done interrupt. */
#define CSR8_TXDONE_ATIMRING		FIELD32(4, 0x00000010)		/* atim ring transmit done interrupt. */
#define CSR8_TXDONE_PRIORING		FIELD32(5, 0x00000020)		/* priority ring transmit done interrupt. */
#define CSR8_RXDONE			FIELD32(6, 0x00000040)		/* receive done interrupt. */
#define CSR8_DECRYPTION_DONE		FIELD32(7, 0x00000080)		/* Decryption done interrupt. */
#define CSR8_ENCRYPTION_DONE		FIELD32(8, 0x00000100)		/* Encryption done interrupt. */
#define CSR8_UART1_TX_TRESHOLD		FIELD32(9, 0x00000200)		/* UART1 TX reaches threshold. */
#define CSR8_UART1_RX_TRESHOLD		FIELD32(10, 0x00000400)		/* UART1 RX reaches threshold. */
#define CSR8_UART1_IDLE_TRESHOLD	FIELD32(11, 0x00000800)		/* UART1 IDLE over threshold. */
#define CSR8_UART1_TX_BUFF_ERROR	FIELD32(12, 0x00001000)		/* UART1 TX buffer error. */
#define CSR8_UART1_RX_BUFF_ERROR	FIELD32(13, 0x00002000)		/* UART1 RX buffer error. */
#define CSR8_UART2_TX_TRESHOLD		FIELD32(14, 0x00004000)		/* UART2 TX reaches threshold. */
#define CSR8_UART2_RX_TRESHOLD		FIELD32(15, 0x00008000)		/* UART2 RX reaches threshold. */
#define CSR8_UART2_IDLE_TRESHOLD	FIELD32(16, 0x00010000)		/* UART2 IDLE over threshold. */
#define CSR8_UART2_TX_BUFF_ERROR	FIELD32(17, 0x00020000)		/* UART2 TX buffer error. */
#define CSR8_UART2_RX_BUFF_ERROR	FIELD32(18, 0x00040000)		/* UART2 RX buffer error. */
#define CSR8_TIMER_CSR3_EXPIRE		FIELD32(19, 0x00080000)		/* TIMECSR3 timer expired (802.1H quiet period). */

/*
 * CSR9: Maximum frame length register.
 */
#define CSR9_MAX_FRAME_UNIT		FIELD32(7, 0x00000f80)		/* maximum frame length in 128b unit, default: 12. */

/*
 * SECCSR0: WEP control register.
 */
#define SECCSR0_KICK_DECRYPT		FIELD32(0, 0x00000001)		/* Kick decryption engine, self-clear. */
#define SECCSR0_ONE_SHOT		FIELD32(1, 0x00000002)		/* 0: ring mode, 1: One shot only mode. */
#define SECCSR0_DESC_ADDRESS		FIELD32(2, 0xfffffffc)		/* Descriptor physical address of frame. */

/*
 * CSR11: Back-off control register.
 */
#define CSR11_CWMIN			FIELD32(0, 0x0000000f)		/* CWmin. Default cwmin is 31 (2^5 - 1). */
#define CSR11_CWMAX			FIELD32(4, 0x000000f0)		/* CWmax. Default cwmax is 1023 (2^10 - 1). */
#define CSR11_SLOT_TIME			FIELD32(8, 0x00001f00)		/* slot time, default is 20us for 802.11b */
#define CSR11_CW_SELECT			FIELD32(13, 0x00002000)		/* CWmin/CWmax selection, 1: Register, 0: TXD. */
#define CSR11_LONG_RETRY		FIELD32(16, 0x00ff0000)		/* long retry count. */
#define CSR11_SHORT_RETRY		FIELD32(24, 0xff000000)		/* short retry count. */

/*
 * CSR12: Synchronization configuration register 0.
 * All units in 1/16 TU.
 */
#define CSR12_BEACON_INTERVAL		FIELD32(0, 0x0000ffff)		/* beacon interval, default is 100 TU. */
#define CSR12_CFPMAX_DURATION		FIELD32(16, 0xffff0000)		/* cfp maximum duration, default is 100 TU. */

/*
 * CSR13: Synchronization configuration register 1.
 * All units in 1/16 TU.
 */
#define CSR13_ATIMW_DURATION		FIELD32(0, 0x0000ffff)		/* atim window duration. */
#define CSR13_CFP_PERIOD		FIELD32(16, 0x00ff0000)		/* cfp period, default is 0 TU. */

/*
 * CSR14: Synchronization control register.
 */
#define CSR14_TSF_COUNT			FIELD32(0, 0x00000001)		/* enable tsf auto counting. */
#define CSR14_TSF_SYNC			FIELD32(1, 0x00000006)		/* tsf sync, 0: disable, 1: infra, 2: ad-hoc mode. */
#define CSR14_TBCN			FIELD32(3, 0x00000008)		/* enable tbcn with reload value. */
#define CSR14_TCFP			FIELD32(4, 0x00000010)		/* enable tcfp & cfp / cp switching. */
#define CSR14_TATIMW			FIELD32(5, 0x00000020)		/* enable tatimw & atim window switching. */
#define CSR14_BEACON_GEN		FIELD32(6, 0x00000040)		/* enable beacon generator. */
#define CSR14_CFP_COUNT_PRELOAD		FIELD32(8, 0x0000ff00)		/* cfp count preload value. */
#define CSR14_TBCM_PRELOAD		FIELD32(16, 0xffff0000)		/* tbcn preload value in units of 64us. */

/*