prev_cmp_d.tan.qmsg

VHDL的D触发器,简明了

{ "Info" "ITDB_TSU_RESULT" "q~reg0 d clk 3.670 ns register " "Info: tsu for register \"q~reg0\" (data pin = \"d\", clock pin = \"clk\") is 3.670 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.632 ns + Longest pin register " "Info: + Longest pin to register delay is 6.632 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns d 1 PIN PIN_31 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_31; Fanout = 1; PIN Node = 'd'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { d } "NODE_NAME" } } { "d.vhd" "" { Text "C:/Documents and Settings/Calvin/桌面/111/d.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.048 ns) + CELL(0.115 ns) 6.632 ns q~reg0 2 REG LC_X1_Y2_N2 1 " "Info: 2: + IC(5.048 ns) + CELL(0.115 ns) = 6.632 ns; Loc. = LC_X1_Y2_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.163 ns" { d q~reg0 } "NODE_NAME" } } { "d.vhd" "" { Text "C:/Documents and Settings/Calvin/桌面/111/d.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 23.88 % ) " "Info: Total cell delay = 1.584 ns ( 23.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.048 ns ( 76.12 % ) " "Info: Total interconnect delay = 5.048 ns ( 76.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.632 ns" { d q~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.632 ns" { d {} d~out0 {} q~reg0 {} } { 0.000ns 0.000ns 5.048ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "d.vhd" "" { Text "C:/Documents and Settings/Calvin/桌面/111/d.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.999 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_33 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_33; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "d.vhd" "" { Text "C:/Documents and Settings/Calvin/桌面/111/d.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.819 ns) + CELL(0.711 ns) 2.999 ns q~reg0 2 REG LC_X1_Y2_N2 1 " "Info: 2: + IC(0.819 ns) + CELL(0.711 ns) = 2.999 ns; Loc. = LC_X1_Y2_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.530 ns" { clk q~reg0 } "NODE_NAME" } } { "d.vhd" "" { Text "C:/Documents and Settings/Calvin/桌面/111/d.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 72.69 % ) " "Info: Total cell delay = 2.180 ns ( 72.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.819 ns ( 27.31 % ) " "Info: Total interconnect delay = 0.819 ns ( 27.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clk q~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clk {} clk~out0 {} q~reg0 {} } { 0.000ns 0.000ns 0.819ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.632 ns" { d q~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.632 ns" { d {} d~out0 {} q~reg0 {} } { 0.000ns 0.000ns 5.048ns } { 0.000ns 1.469ns 0.115ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clk q~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clk {} clk~out0 {} q~reg0 {} } { 0.000ns 0.000ns 0.819ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q q~reg0 6.491 ns register " "Info: tco from clock \"clk\" to destination pin \"q\" through register \"q~reg0\" is 6.491 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.999 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_33 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_33; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "d.vhd" "" { Text "C:/Documents and Settings/Calvin/桌面/111/d.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.819 ns) + CELL(0.711 ns) 2.999 ns q~reg0 2 REG LC_X1_Y2_N2 1 " "Info: 2: + IC(0.819 ns) + CELL(0.711 ns) = 2.999 ns; Loc. = LC_X1_Y2_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.530 ns" { clk q~reg0 } "NODE_NAME" } } { "d.vhd" "" { Text "C:/Documents and Settings/Calvin/桌面/111/d.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 72.69 % ) " "Info: Total cell delay = 2.180 ns ( 72.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.819 ns ( 27.31 % ) " "Info: Total interconnect delay = 0.819 ns ( 27.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clk q~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clk {} clk~out0 {} q~reg0 {} } { 0.000ns 0.000ns 0.819ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "d.vhd" "" { Text "C:/Documents and Settings/Calvin/桌面/111/d.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.268 ns + Longest register pin " "Info: + Longest register to pin delay is 3.268 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q~reg0 1 REG LC_X1_Y2_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q~reg0 } "NODE_NAME" } } { "d.vhd" "" { Text "C:/Documents and Settings/Calvin/桌面/111/d.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.144 ns) + CELL(2.124 ns) 3.268 ns q 2 PIN PIN_34 0 " "Info: 2: + IC(1.144 ns) + CELL(2.124 ns) = 3.268 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'q'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.268 ns" { q~reg0 q } "NODE_NAME" } } { "d.vhd" "" { Text "C:/Documents and Settings/Calvin/桌面/111/d.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 64.99 % ) " "Info: Total cell delay = 2.124 ns ( 64.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.144 ns ( 35.01 % ) " "Info: Total interconnect delay = 1.144 ns ( 35.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.268 ns" { q~reg0 q } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.268 ns" { q~reg0 {} q {} } { 0.000ns 1.144ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clk q~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clk {} clk~out0 {} q~reg0 {} } { 0.000ns 0.000ns 0.819ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.268 ns" { q~reg0 q } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.268 ns" { q~reg0 {} q {} } { 0.000ns 1.144ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "q~reg0 d clk -3.618 ns register " "Info: th for register \"q~reg0\" (data pin = \"d\", clock pin = \"clk\") is -3.618 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.999 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_33 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_33; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "d.vhd" "" { Text "C:/Documents and Settings/Calvin/桌面/111/d.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.819 ns) + CELL(0.711 ns) 2.999 ns q~reg0 2 REG LC_X1_Y2_N2 1 " "Info: 2: + IC(0.819 ns) + CELL(0.711 ns) = 2.999 ns; Loc. = LC_X1_Y2_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.530 ns" { clk q~reg0 } "NODE_NAME" } } { "d.vhd" "" { Text "C:/Documents and Settings/Calvin/桌面/111/d.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 72.69 % ) " "Info: Total cell delay = 2.180 ns ( 72.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.819 ns ( 27.31 % ) " "Info: Total interconnect delay = 0.819 ns ( 27.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clk q~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clk {} clk~out0 {} q~reg0 {} } { 0.000ns 0.000ns 0.819ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "d.vhd" "" { Text "C:/Documents and Settings/Calvin/桌面/111/d.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.632 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.632 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns d 1 PIN PIN_31 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_31; Fanout = 1; PIN Node = 'd'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { d } "NODE_NAME" } } { "d.vhd" "" { Text "C:/Documents and Settings/Calvin/桌面/111/d.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.048 ns) + CELL(0.115 ns) 6.632 ns q~reg0 2 REG LC_X1_Y2_N2 1 " "Info: 2: + IC(5.048 ns) + CELL(0.115 ns) = 6.632 ns; Loc. = LC_X1_Y2_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.163 ns" { d q~reg0 } "NODE_NAME" } } { "d.vhd" "" { Text "C:/Documents and Settings/Calvin/桌面/111/d.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 23.88 % ) " "Info: Total cell delay = 1.584 ns ( 23.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.048 ns ( 76.12 % ) " "Info: Total interconnect delay = 5.048 ns ( 76.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.632 ns" { d q~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.632 ns" { d {} d~out0 {} q~reg0 {} } { 0.000ns 0.000ns 5.048ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clk q~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clk {} clk~out0 {} q~reg0 {} } { 0.000ns 0.000ns 0.819ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.632 ns" { d q~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.632 ns" { d {} d~out0 {} q~reg0 {} } { 0.000ns 0.000ns 5.048ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "109 " "Info: Allocated 109 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 15 21:32:27 2008 " "Info: Processing ended: Thu May 15 21:32:27 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}