dct2d.v

2维DCt源码

module dct2d(
			clk,
			rst,
			
			in_data_1,
			in_data_2,
			in_data_3,
			in_data_4,
			in_data_5,
			in_data_6,
			in_data_7,
			in_data_8,
			
			out_data_1,
			out_data_2,
			out_data_3,
			out_data_4,
			out_data_5,
			out_data_6,
			out_data_7,
			out_data_8,
			
			out_ena,
			
			dct_start,
			dct_busy,
			
			qnr_start,
			qnr_busy
			);

input clk;
input rst;

input [15:0] in_data_1,in_data_2,in_data_3,in_data_4,in_data_5,in_data_6,in_data_7,in_data_8;
output [15:0] out_data_1,out_data_2,out_data_3,out_data_4,out_data_5,out_data_6,out_data_7,out_data_8;

input dct_start;
output dct_busy;

output qnr_start;
input qnr_busy;
output out_ena;

reg out_ena;
reg dct_busy;
reg qnr_start;

wire [15:0] di_1,di_2,di_3,di_4,di_5,di_6,di_7,di_8;
wire [15:0] do_1,do_2,do_3,do_4,do_5,do_6,do_7,do_8;

reg [15:0] mat_data [63:0];

reg [7:0] count;
reg qnr_busy_d;
reg dim;
reg dct_ena;
reg input_ena;
reg convert_ena;


integer i;

dct			u1(
			.clk(clk),
			.rst(rst),
			.di_1(di_1),.di_2(di_2),.di_3(di_3),.di_4(di_4),.di_5(di_5),.di_6(di_6),.di_7(di_7),.di_8(di_8),
			.do_1(do_1),.do_2(do_2),.do_3(do_3),.do_4(do_4),.do_5(do_5),.do_6(do_6),.do_7(do_7),.do_8(do_8),
			.ena(dct_ena)
			);

assign out_data_1 = do_1;
assign out_data_2 = do_2;
assign out_data_3 = do_3;
assign out_data_4 = do_4;
assign out_data_5 = do_5;
assign out_data_6 = do_6;
assign out_data_7 = do_7;
assign out_data_8 = do_8;

assign di_1 = ~dim ? in_data_1 : mat_data[56];
assign di_2 = ~dim ? in_data_2 : mat_data[48];
assign di_3 = ~dim ? in_data_3 : mat_data[40];
assign di_4 = ~dim ? in_data_4 : mat_data[32];
assign di_5 = ~dim ? in_data_5 : mat_data[24];
assign di_6 = ~dim ? in_data_6 : mat_data[16];
assign di_7 = ~dim ? in_data_7 : mat_data[8];
assign di_8 = ~dim ? in_data_8 : mat_data[0];

always @(negedge rst or posedge clk)
begin
	if(rst==0)
		count<=8'b0;
	else if(dct_busy==1)
			count<=count+8'b01;
	else
			count<=8'b0;
end

always @(negedge rst or posedge clk)
begin
	if(rst==0)
		dct_busy<=0;
	else if(dct_start==1)
			dct_busy<=1;
	else if(~qnr_busy && qnr_busy_d)
			dct_busy<=0;
end

always @(negedge rst or posedge clk)
begin
	if(rst==0)
		qnr_busy_d<=0;
	else 
		qnr_busy_d<=qnr_busy;
end

always @(negedge rst or posedge clk)
begin
	if(rst==0)
		for(i=0;i<64;i=i+1)
			mat_data[i]<=16'b0;
	else if(input_ena==1)
			begin
				for(i=63;i>7;i=i-1)
					mat_data[i]<=mat_data[i-8];
				mat_data[0] <= do_1;
				mat_data[1] <= do_2;
				mat_data[2] <= do_3;
				mat_data[3] <= do_4;
				mat_data[4] <= do_5;
				mat_data[5] <= do_6;
				mat_data[6] <= do_7;
				mat_data[7] <= do_8;	
			end
	else if(convert_ena==1)
			for(i=0;i<7;i=i+1)
			begin
				mat_data[i]<=mat_data[i+1];
				mat_data[i+8]<=mat_data[i+1+8];
				mat_data[i+16]<=mat_data[i+1+16];
				mat_data[i+24]<=mat_data[i+1+24];
				mat_data[i+32]<=mat_data[i+1+32];
				mat_data[i+40]<=mat_data[i+1+40];
				mat_data[i+48]<=mat_data[i+1+48];
				mat_data[i+56]<=mat_data[i+1+56];	
			end
end

always @(negedge rst or posedge clk)
begin
	if(rst==0)
		dct_ena<=0;
	else if(dct_busy==1)
			begin
			if(count==8'b0)
				dct_ena<=1;
			else if(count==25)
					dct_ena<=0;
			end
	else
			dct_ena<=0;
end

always @(negedge rst or posedge clk)
begin
	if(rst==0)
		input_ena<=0;
	else if(dct_busy==1)
			begin
			if(count==4)
				input_ena<=1;
			else if(count==12)
					input_ena<=0;
			end
	else
			input_ena<=0;
end

always @(negedge rst or posedge clk)
begin
	if(rst==0)
		convert_ena<=0;
	else if(dct_busy==1)
			begin
			if(count==13)
				convert_ena<=1;
			else if(count==21)
					convert_ena<=0;
			end
	else
			convert_ena<=0;
end

always @(negedge rst or posedge clk)
begin
	if(rst==0)
		dim<=0;
	else if(dct_busy==1)
			begin
			if(count==12)
				dim<=1;
			else if(count==25)
					dim<=0;
			end
	else
			dim<=0;
end

always @(negedge rst or posedge clk)
begin
	if(rst==0)
		out_ena<=0;
	else if(dct_busy==1)
			begin
			if(count==17)
				out_ena<=1;
			else if(count==25)
					out_ena<=0;
			end
	else
			out_ena<=0;
end

always @(negedge rst or posedge clk)
begin
	if(rst==0)
		qnr_start<=0;
	else if(dct_busy==1)
			begin
			if(count==26)
				qnr_start<=1;
			end
	else
			qnr_start<=0;
end

endmodule