📄 led.v
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module led(
clk,
rst,
di_1,di_2,di_3,di_4,di_5,
di_6,di_7,di_8,di_9,di_10,
dout,
chip_sel);
input clk;
input rst;
input [7:0] di_1,di_2,di_3,di_4,di_5;
input [7:0] di_6,di_7,di_8,di_9,di_10;
output [7:0] dout;
output [9:0] chip_sel;
reg [3:0] i;
reg [9:0] temp_bit_dat;
reg [7:0] seg_data_tmp;
assign dout = seg_data_tmp;
assign chip_sel = temp_bit_dat;
always @(negedge rst or posedge clk)
begin
if(rst==0)
i=0;
else if(i==9)
i<=0;
else
i<=i+1;
end
always @(negedge rst or posedge clk)
begin
if(rst==0)
begin
seg_data_tmp<=8'b0;
end
else
case (i)
4'd0:seg_data_tmp=di_1;
4'd1:seg_data_tmp=di_2;
4'd2:seg_data_tmp=di_3;
4'd3:seg_data_tmp=di_4;
4'd4:seg_data_tmp=di_5;
4'd5:seg_data_tmp=di_6;
4'd6:seg_data_tmp=di_7;
4'd7:seg_data_tmp=di_8;
4'd8:seg_data_tmp=di_9;
4'd9:seg_data_tmp=di_10;
default:seg_data_tmp=8'b0;
endcase
end
always @(negedge rst or posedge clk)
begin
if(rst==0)
begin
temp_bit_dat<=10'b0;
end
else
case (i)
4'd0:temp_bit_dat=10'b0000000001;
4'd1:temp_bit_dat=10'b0000000010;
4'd2:temp_bit_dat=10'b0000000100;
4'd3:temp_bit_dat=10'b0000001000;
4'd4:temp_bit_dat=10'b0000010000;
4'd5:temp_bit_dat=10'b0000100000;
4'd6:temp_bit_dat=10'b0001000000;
4'd7:temp_bit_dat=10'b0010000000;
4'd8:temp_bit_dat=10'b0100000000;
4'd9:temp_bit_dat=10'b1000000000;
default:temp_bit_dat=10'b0000000000;
endcase
end
endmodule
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