test.v

来自「10位8段LED的扫描显示程序」· Verilog 代码 · 共 58 行

`timescale 1 ns / 1 ns


module test();


reg rst;
reg clk;

reg [7:0] d1,d2,d3,d4,d5,d6,d7,d8,d9,d10;
wire [7:0] dout;
wire [9:0] chip_sel;

led		u1(
		.clk(clk),
		.rst(rst),
		
		.di_1(d1),.di_2(d2),.di_3(d3),.di_4(d4),.di_5(d5),
		.di_6(d6),.di_7(d7),.di_8(d8),.di_9(d9),.di_10(d10),
		
		.dout(dout),
		.chip_sel(chip_sel));
		
always
begin
	clk=0;
	#12;
	clk=1;
	#13;
end

initial 
begin
	rst=0;
	#500;
	rst=1;
end

initial
begin
	d1=0;
	d2=1;
	d3=2;
	d4=3;
	d5=4;
	d6=5;
	d7=6;
	d8=7;
	d9=8;
	d10=9;
end

initial 
begin
	#1000000 $stop;
end

endmodule