pci9030.v

来自「pci9030接口」· Verilog 代码 · 共 77 行

module pci9030(	rst,
				clk,
				ads,
				la,
				ld,
				blast,
				wr,
				rd,
				lwr,
				ready,
				rxdram_r,
				rxdram_addr,
				rxdram_data,
				txdram_w,
				txdram_addr,
				txdram_data,
				rx_byte_count_l,	//npu to host rx data length low byte
				rx_byte_count_h,	//npu to host rx data length high byte
				rx_npu_state,		//npu to host rx state
				host_rx_state,		//host to npu rx state
				host_tx_state,		//host to npu tx state
				tx_npu_state,		//npu to host tx state
				tx_byte_count_l,	//host to npu tx data length low byte
				tx_byte_count_h		//host to npu tx data length high byte
				);
				

input rst;
input clk;
input ads;
input [27:2] la;
input [31:0] ld;
input blast;
input wr;
input rd;
input lwr;
output ready;
output rxdram_r;
output [10:0] rxdram_addr;
input [7:0] rxdram_data;
output txdram_w;
output [10:0] txdram_addr;
output [7:0] txdram_data;
input [7:0] rx_byte_count_l;			//npu to host rx data length low byte
input [7:0] rx_byte_count_h;			//npu to host rx data length high byte
input [7:0] rx_npu_state;				//npu to host rx state
output [7:0] host_rx_state;				//host to npu rx state
output [7:0] host_tx_state;				//host to npu tx state
input [7:0] tx_npu_state;				//npu to host tx state
output [7:0] tx_byte_count_l;			//host to npu tx data length low byte
output [7:0] tx_byte_count_h;			//host to npu tx data length high byte


reg ads_1,ads_2;


always @(negedge rst or posedge clk)
begin
	if(rst==0)
		begin
			ads_1<=1;
			ads_2<=0;
		end
	else
		begin
			ads_1<=ads;
			ads_2<=ads_1;
		end
end

always @(negedge rst or posedge clk)
begin
	if(rst==0)
		
end

endmodule